MC145574APB Freescale Semiconductor, MC145574APB Datasheet - Page 35

• Manufacturer Part Number: MC145574APB
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574APB

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
4.3.6.7
4.3.6.8
4.3.6.9
TSEN Signal
The TSEN signal is enabled via the SCP. See description for OR7 bits 1 and 0. This pin then becomes
an open drain output that pulls low when data is being output from D out . This signal can then be used
to enable an external driver in applications where the IDL2 data goes off–board, such as PBXs, channel
banks, etc.
Miscellaneous
Clock Options
In the slave mode, the IDL2 interface accepts any clock from 512 kHz to 4096 kHz in 8 kHz increments.
In the master mode, the DCL has four frequency options, programmable through the SCP. The clock
rate can be either 2.56 MHz, 2.048 MHz, 1.536 MHz, or 512 kHz. The default selection is 2.56 MHz.
B Channel Exchange
An option is provided to exchange the B1 and B2 channels inside the IDL2. This exchange operates
simultaneously in both Tx and Rx directions.
B1 and B2 Blocking
Options are provided to independently block or force the B1 and B2 channels to all ones in both the
transmit and receive directions.
B1 and B2 Inversion
Options are provided to independently invert the B1 and B2 channels in both the transmit and receive
directions.
B1, B2, and D Loopbacks
Options are provided to make an individual loopback on each B1, B2, or D channel.
IDL2 Waveform Diagrams
The relative timing relationships of the IDL2 signals are shown in Figures 4–5 through 4–8.
MC145574
4–9