MC145574APB Freescale Semiconductor, MC145574APB Datasheet - Page 115

• Manufacturer Part Number: MC145574APB
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574APB

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
15.1
15.2
15.3
15.4
INTRODUCTION
When the MC145574 in SCP is configured as a TE, it has three interrupt modes. When the MC145574
is configured as an NT, it has four interrupt modes. Each of these interrupts is maskable. When an
interrupt occurs (and if the interrupt condition is enabled), the MC145574 asserts the IRQ pin. A detailed
description of these interrupts, and how they are cleared, follows.
IRQ7
IRQ7 is used in the NT Terminal mode of the MC145574 to indicate that a collision has occurred on
the D channel. This bit operates in the same manner as the IRQ1 interrupt in TE mode, and likewise
is cleared by writing a 0 to the NR3(0) bit. This action also releases the IRQ pin.
Note that this bit is maskable by means of NR4(0). This interrupt is only applicable in the NT mode
and is therefore not available in the TE mode.
IRQ1
IRQ1 is used in the TE mode of operation of the MC145574 to indicate to external devices that a
collision has occurred on the D channel. A D channel collision is considered to have occurred when
the TE is transmitting on the D channel (both DREQUEST and DGRANT being high) and the received
E echo bit from the NT does not match the previously modulated D bit. When IRQ1 occurs, the
MC145574 internally sets NR3(1) to a 1. If the IRQ1 ENABLE is set to 1, an interrupt to an external
device is generated. The interrupt condition is cleared by writing a 0 to NR3(1). Note that this bit is
maskable by means of NR4(1). This interrupt is only applicable in the TE mode and is therefore not
available in the NT mode.
IRQ2
IRQ2 is provided for multiframing reception indication. This interrupt is applicable and available in
both NT and TE modes of operation of the MC145574. Note that this interrupt is maskable by means
of NR4(2). Multiframing is initiated by the NT by setting BR7(5). A multiframe is 20 basic frames, or
5 ms in duration. If this interrupt is enabled (it is enabled by setting NR4(2)) and if multiframing is
in progress, then an interrupt is generated on multiframe boundaries; i.e., every 5 ms. Alternatively,
an NT–configured MC145574 can be programmed to generate an interrupt only in the event of a new
Q channel nibble having been received. Similarly, a TE–configured MC145574 can be programmed
to generate an interrupt only in the event of a new SC1 subchannel having been received. Refer to
Section 12 for a detailed description of these features.
If an interrupt is to occur, it will do so in the 47th baud of the transmitted frame of the 20th frame
in a multiframe. Data to be transmitted in the SC1 through SC5 subchannels in the NT is internally
latched from BR2(7:4), BR9(7:0), and BR10(7:0) during the 47th baud of the transmitted frame of
the 20th frame in a multiframe. At this time, the received Q channel nibble is made available by internally
NR3(0)
NR4(0)
NR3(1)
NR4(1)
NR3(2)
NR4(2)
NT : D CHANNEL COLLISION
TE : NOT APPLICABLE
ENABLE
TE: D CHANNEL COLLISION
NT: NOT APPLICABLE
ENABLE
MULTIFRAME RECEPTION
ENABLE
MC145574
INTERRUPTS
15
15–1