CY7B9234-270JXC Cypress Semiconductor Corp, CY7B9234-270JXC Datasheet - Page 21

• Manufacturer Part Number: CY7B9234-270JXC
• Description: IC TRANSMITTER HOTLINK 28-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink™r
• Type: Transmitter and Receiverr

Specifications of CY7B9234-270JXC

• Package / Case: 28-PLCC
• Protocol: Fibre Channel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: PHY
• Supply Voltage (min): 4.5 V
• Supply Current: 0.085 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2905-5; CY7B9234-270JXC

external to SMPTE HOTLink. This data can use any encoding
method suitable to the designer. The only restrictions upon the
data encoding method is that it contain suitable transition density
for the Receiver PLL data synchronizer (one per 10 bit byte) and
that it be compatible with the transmission media.
The framer function in Bypass mode is identical to Encoded
mode, so a K28.5 pattern can still be used to re-frame the serial
bit stream.
Parallel Output Function
The 10 outputs (Q
neously, and are aligned with RDY and CKR with timing allow-
ances to interface directly with either an asynchronous FIFO or
a clocked FIFO. Typical FIFO connections are shown in Figure 5.
Data outputs can be clocked into the system using either the
rising or falling edge of CKR, or the rising or falling edge of RDY.
If CKR is used, RDY can be used as an enable for the receiving
logic. A LOW pulse on RDY shows that new data has been
received and is ready to be delivered. The signal on RDY is a
60%-LOW duty cycle byte-rate pulse train suitable for the write
pulse in asynchronous FIFOs such as the CY7C42X, or the
enable write input on Clocked FIFOs such as the CY7C44X.
HIGH on RDY shows that the received data appearing at the
outputs is the null character (normally inserted by the transmitter
as a pad between data inputs) and should be ignored.
When the Transmitter is disabled it will continuously send pad
characters (K28.5). To assure that the receive FIFO will not be
overfilled with these dummy bytes, the RDY pulse output is
inhibited during fill strings. Data at the Q
the correct received data, but will not appear to change, since a
string of K28.5s all are decoded as Q7−0 =000 00101 and SC/D
= 1 (C5.0). When new data appears (not K28.5), the RDY output
will resume normal function. The “last” K28.5 will be accom-
panied by a normal RDY pulse.
Fill characters are defined as any K28.5 followed by another
K28.5. All fill characters will not cause RDY to pulse. Any K28.5
followed by any other character (including violation or illegal
characters) will be interpreted as usable data and will cause RDY
to pulse.
As noted above, RDY can also be used as an indication of
correct framing of received data. While the Receiver is awaiting
receipt of a K28.5 with RF HIGH, the RDY outputs will be
inhibited. When RDY resumes, the received data will be properly
framed and will be decoded correctly. In Bypass mode with RF
HIGH, RDY will pulse once for each K28.5 received. For more
information on the RDY pin, consult the “HOTLink CY7B933
RDY Pin Description” application note.
Code rule violations and reception errors will be indicated as
follows:
Document #: 38-02014 Rev. *B
0−7
, SC/D, and RVS) all transition simulta-
0−7
outputs will reflect
Receiver Serial Data Requirements
The CY7B9334 SMPTE HOTLink Receiver serial input capability
conforms to the requirements of the Fibre Channel specification.
The serial data input is tracked by an internal Phase-Locked
Loop that is used to recover the clock phase and to extract the
data from the serial bit-stream. Jitter tolerance characteristics
(including both PLL and logic component requirements) are
shown below:
■
■
■
■
Receiver Test Mode Description
The CY7B9334 Receiver offers two types of test mode
operation, BIST mode and Test mode. In a normal system appli-
cation, the Built-In Self-Test (BIST) mode can be used to check
the functionality of the Transmitter, the Receiver and the link
connecting them. This mode is available with minimal impact on
user system logic, and can be used as part of the normal system
diagnostics. Typical connections and timing are shown in
Figure 7.
1. Good Data code received
2. Good Special Character
3. K28.7 immediately following
4. K28.7 immediately following
5. Unassigned code received
6. −K28.5+ received when
7. +K28.5− received when
8. Good code received
Deterministic Jitter tolerance (D
measured while receiving data carried by a bandwidth-limited
channel (e.g., a coaxial transmission line) while maintaining a
Bit Error Rate (BER) <10
Random Jitter tolerance (R
while receiving data carried by a random-noise-limited channel
(e.g., a fiber-optic transmission system with low light levels)
while maintaining a Bit Error Rate (BER) <10
Total Jitter tolerance >90% of t
PLL-Acquisition time <500-bit times from worst-case phase or
frequency change in the serial input data stream, to receiving
data within BER objective of 10
within specifications, stable REFCLK input frequency and
normal data framing protocols are assumed. Note: Acquisition
time is measured from worst-case phase or frequency change
to zero phase and frequency error. As a result of the receiver’s
wide jitter tolerance, valid data will appear at the receiver’s
outputs a few byte times after a worst-case phase change.
with good Running Disparity
(RD)
code received with good RD
K28.1 (ESCON Connect_SOF)0
K28.5 (ESCON Passive_SOF)
RD was +
RD was −
with wrong RD
−12
j
) > 90% of t
.
RVS SC/D Qouts Name
B
−12
j
. Total of D
1
) >40% of t
. Stable power supplies
0
0
0
1
1
1
1
B
. Typically measured
100−0B C0.0−11.0
127
147
E0
1E4
000−FF D0.0−31.7
1E1
1E2
j
B
+ R
CY7B9234
CY7B9334
. Typically
−12
j
Page 21 of 36
.
.
C7.1
C7.2
C0.7
C1.7
C2.7
C4.7
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