E-ST7538P STMicroelectronics, E-ST7538P Datasheet

Page 1

... It operates from a single supply voltage and integrates a line driver and a 5V linear regulator. The device oper- ation is controlled by means of an internal register, programmable through the synchronous serial in- terface. Additional functions as watchdog, clock output, output voltage and current control, pream- ble detection, time-out, band in use are included ...

Page 2

... Time Out Event Occurred "0" Time-out Event Occurred Synchronous Mains Access Clock or Control Register Access Clock Band in use Output. "1" Signal within the Programmed Band "0" No Signal within the Programmed Band Digital Supply Voltage Master Clock Output Power On or Watchdog Reset Output VDC 33 ...

Page 3

... Cannot be left floating <4> If not used this pin must be connected to VDC <5> If not used this pin must be tied low (SGND or PAVss or DVss) Description Test Input. Must be connected to DVss during Normal Operation Watchdog input. The Internal Watchdog Counter is cleared on the falling edges. ...

Page 4

... Maximum Thermal Resistance Junction-Ambient Steady State(*) th-j-amb1 R Maximum Thermal Resistance Junction-Ambient Steady State(**) th-j-amb2 (*) Mounted on Multilayer PCB with a dissipating surface on the bottom side of the PCB (**) It's the same condition of the point above, without any heatsinking surface on the board. 4/30 Parameter and ...

Page 5

... Table 5. Electrical Characteristcs (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85° 86kHz, other Control Register parameters as default value, unless otherwise specified). Symbol Parameter AV , Supply Voltages PAV - DV PAV and DV Relation during Power-Up Sequence PAV - AV PAV and DV Relation ...

Page 6

... ST7538 Table 5. Electrical Characteristcs (continued) (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85° 86kHz, other Control Register parameters as default value, unless otherwise specified). Symbol Parameter V Max Carrier Output AC Voltage ATOP(AC) for each ATOP1 and ATOP2 pins ...

Page 7

... Table 5. Electrical Characteristcs (continued) (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85° 86kHz, other Control Register parameters as default value, unless otherwise specified). Symbol Parameter R Input Impedance IN V Carrier Detection Sensitivity CD (Normal Mode) Carrier Detection Sensitivity (High Sensitivity Mode) ...

Page 8

... ST7538 Table 5. Electrical Characteristcs (continued) (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85° 86kHz, other Control Register parameters as default value, unless otherwise specified). Symbol Parameter T Baud rate Bit Time (=1/ B Zero Crossing Detection ZC Zero Crossing Detection delay ...

Page 9

... ST7538 is a multi frequency device: eight programmable Carrier Frequencies are available (see table 6). Only one Carrier at a time can be used; anyway, it's possible to switch the communication channel during the normal working Mode. Selecting the desired frequency in the Control Register the Transmission and Reception filters are accordingly tuned ...

Page 10

... Mark and Space Communication Frequencies are defined by the following formula: ∆F F ("0") = FCarrier + [ ]/2 ∆F F ("1") = FCarrier - [ ]/2 ∆F(Frequency Deviation) = Deviation*BAUD rate. Here follows a table listing the correlation between frequency parameters and actual tones frequencies. Table 8. ST7538 synthesized frequencies Carrier Baud Frequency Deviation Rate (KHz) ...

Page 11

... Data are exchange without any auxiliary Clock reference in an Asynchronous mode without adding any protocol bits. The host controller has to recover the clock reference in receiving Mode and control the Bit time in transmission mode. RxD line is forced to a low logic level when no carrier is detected. ...

Page 12

... T line. When ST7538 is in receiving mode an internal PLL recovers the clock reference. Data on RxD line are stable on CLR/T rising Edge. When ST7538 is in transmitting mode the clock reference is internally generated and data are read on TxD line on CLR/T rising Edge. If line is set to “1” & REG_DATA=”0” (Data Reception), ST7538 enters in an Idle State and CLR/T RxTx line is forced Low ...

Page 13

... Figure 10. Data Transmission CLR_T T B TXD REG_DATA RxTx RXD ➨ Data Reception Timing Diagram BIT23 BIT22 ➨ Data Reception Timing Diagram BIT23 BIT22 Control Register read Data Reception Timing Diagram ➨ ➨ BIT23 BIT22 Control Register Write ➨ ➨ BIT23 BIT22 ...

Page 14

... RX Logic for final digital filtering. Digital filtering Removes Noise spikes far from the BAUD rate frequency and Reduces the Signal Jitter. RxD Line is forced at logic level “0” when neither mark or space frequencies are detected on RAI Pin. ...

Page 15

... Preamble Detection CARRIER DETECTION: The Carrier/Preamble detection Block notifies to the host controller the presence of a Carrier when it detects on the RAI Input a signal with an harmonic component close to the programmed Carrier Frequency. The CD_PD signal sensitivity is identical to the data reception sensitivity (0.5mVrms Typ. in Normal Sensitivity Mode). ...

Page 16

... The frequencies Table in different Configuration is reported in Table 8. The fre- quencies precision is same as external crystal one’s. In the analog domain, the signal is filtered in order to reduce the output signal spectrum and to reduce the harmonic distortion. The transition between a symbol and the following is done at the end of the on-going half FSK sinewave cycle ...

Page 17

... The Automatic Level Control Block (ALC variable gain amplifier (with 32 non linear discrete steps) controlled by two analog feed backs acting at the same time. The ALC gain range is 0dB and the gain change is clocked at 5KHz. Each step increases or reduces the voltage of 1dB (Typ). ...

Page 18

... The PLI requires, to ensure a proper operation, a regulated and well filtered Supply Voltage. PAVcc Voltage must fulfil the following formula to work without clipping phenomena: To allow the driving of an external Power Line Interface, the output of the ALC is available even on ATO pin. ATO output has a current capability much lower than ATOP1 and ATOP2. ...

Page 19

... Figure 17. PLI Bridge Topology INVERTER ALC Figure 18. PLI Startup Timing Diagram RX/TX ATOP2 ATOP2 ATOP1 Vout R1 Vsense VOLTAGE LOOP 5.6nF R2 CL CURRENT LOOP RCL PAVss D03IN1422 T ALC T T RXTX STEP NUMBER 16 17 LOAD 100pF 18 31 D03IN1408 ST7538 19/30 ...

Page 20

... Figure 19. Typical crystal configuration if ST7538 internal crystal driver circuit is used If an external oscillator is used, XIN must be connected to DVss, while XOUT must satisfy the specifica- tions given in table 5 (see also fig.20). Figure 20. XOUT waveforms if an external oscillator is used (see table 8 for parameter values) ...

Page 21

... Zero Crossing Synchronization ■ Detection Method ■ Mains Interfacing Mode Output Clock ■ Input Pre-Filter ■ ■ Sensitivity Mode Table 11. Control Register Functions Function Frequencies Baud Rate 5 Deviation 6 Watchdog Enabled (1 Transmission Time Out Frequency detection time 11 Zero Crossing Synchronization Value ...

Page 22

... ST7538 Table 11. Control Register Functions (continued) Function Detection Carrier detection Method without conditioning Carrier detection with conditioning Preamble detection without conditioning Preamble detection with conditioning 14 Mains Synchronous Interfacing Asynchronous Mode Output Clock Not Used 21 Reserved 22 Sensitivity Normal Sensitivity Mode High Sensitivity ...

Page 23

... ST7538 to automatically manage the CENELEC Medium Access specification. When a time-out event occur, TOUT is forced high, and is held high for at least 125 ms. To Unlock the Time Out condition should be forced High. During the time out period only register access or reception mode are en- RxTx abled ...

Page 24

... REGOK goes to "1". REGOK function is disabled during a control register writing ses- sion. 4.7 Under Voltage Lock Out The UVLO function turns off the device if the PAVdd voltage falls under 4V. Hysteresis is 340mV typically. 4.8 Thermal Shutdown The ST7538 is provided of a thermal protection which turn off the PLI when the junction temperature ex- ceeds 170° ...

Page 25

... PAVcc rising slope must not exceed 100V/ms. 2) When DVdd and AVdd are below 5V (externally supplied): 100mV < PAVcc-AVdd , PAVcc-DVdd < 1.2V. When AVdd and DVdd supply are connected to VDC, with load < 100mA and filtering capacitor on VDC < 100uF, the second rule can be ignored. Figure 25. Power-UP Sequence ...

Page 26

... ST7538 Figure 26. Application Schematic Example with Coupling Tranformer. 26/30 ...

Page 27

... Moreover it is recomeded to connect the ground layer on the soldering side to another ground layer on the opposite side with vias suggested to not use the PCB surface below the slug area to interconnect any pin except groung pins. Figure 27. ST7538 Slug Drawing Figure 28 ...

Page 28

... ST7538 Figure 29. TQFP44 (Slug Down) Mechanical Data & Package Dimensions mm DIM. MIN. TYP. MAX. A 1.60 A1 0.05 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 D 11.80 12.00 12.20 D1 9.80 10.00 10.20 D3 8.00 e 0.80 E 11.80 12.00 12.20 E1 9.80 10.00 10.20 E3 8. ...

Page 29

... Table 12. Revision History Date Revision January 2004 24-Nov-2005 4 Migration from ST-Press to EDOCS DMS. 5 Removed “Packet Mode” function. Inserted new Paragraph 3.8. on Crystal Oscillator. Added ECOPACK information. Description of Changes ST7538 29/30 ...

Page 30

... STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America ...