DS26519GN+ Maxim Integrated Products, DS26519GN+ Datasheet - Page 251

• Manufacturer Part Number: DS26519GN+
• Description: IC TXRX T1/E1/J1 16PRT 484-HSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26519GN+

• Number Of Drivers/receivers: 16/16
• Protocol: Ethernet
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 484-BGA Exposed Pad, 484-eBGA, 484-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Addresses:
Bit #
Name
Default
Bit 6: Receive Hitless Protection Mode (RHPM)
If the TXENABLE pin is low and this bit is set to one, the receive LIU will present a high impedance to the line,
overriding the receive impedance selection register bits LRISMR.RIMPM[2:0].
Bits 5 and 4 : Jitter Attenuator Depth Select (JADS[1:0])
Bits 3 and 2: Jitter Attenuator Position Select (JAPS[1:0]). These bits are used to select the position of the jitter
attenuator.
Bit 1: T1J1E1 Selection (T1J1E1S). This bit configures the LIU for E1 or T1/J1 operation.
Bit 0: LOS Selection Criteria (LSC). This bit is used for LIU LOS selection criteria.
JADS1
JAPS1
0
0
1
1
0
0
1
1
0 = Normal operation using software for hitless protection (RIMPON).
1 = Hitless protection switching mode using TXENABLE pin.
0 = E1
1 = T1 or J1
E1 Mode
0 = G.775
1 = ETS 300 233
T1/J1 Mode
0 = T1.231
1 = T1.231
JADS0
JAPS0
—
7
0
0
1
0
1
0
1
0
1
Jitter attenuator FIFO depth 128 bits.
Jitter attenuator FIFO depth 64 bits.
Jitter attenuator FIFO depth 32 bits.
Jitter attenuator FIFO depth 16 bits (used for delay sensitive applications).
Jitter attenuator in the receive path.
Jitter attenuator in the transmit path.
Jitter attenuator disabled.
Jitter attenuator disabled.
LTRCR
LIU Transmit Receive Control Register
1000h + (20h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
RHPM
6
0
FUNCTION
JADS1
5
0
251 of 310
JADS0
4
0
FUNCTION
JAPS1
3
0
DS26519 16-Port T1/E1/J1 Transceiver
JAPS0
2
0
T1J1E1S
1
0
LSC
0
0