DS26528GN+ Maxim Integrated Products, DS26528GN+ Datasheet - Page 29

• Manufacturer Part Number: DS26528GN+
• Description: IC TXRX T1/E1/J1 OCT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26528GN+

• Number Of Drivers/receivers: 4/4
• Protocol: IEEE 1149.1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3
A hardware reset is issued by forcing the RESETB pin to logic-low. The RESETB input pin resets all framers, LIUs,
and BERTs. Note that not all registers are cleared to 00h on a reset condition. The register space must be
reinitialized to appropriate values after a hardware or software reset has occurred. This includes writing
reserved locations to 00h.
The DS26528 has several features included to reduce power consumption. The LIU transmitters can be powered
down by setting the TPDE bit in the LIU Maintenance Control register (LMCR). Note that powering down the
transmit LIU results in a high-impedance state for the corresponding TTIP and TRING pins and reduced operating
current. The RPDE bit in the
The TE (transmit enable) bit in the
them in a high-impedance mode, while keeping the LIU in an active state (powered up). This is useful for
equipment protection-switching applications.
Table 8-1. Reset Functions
Hardware Device Reset
Hardware JTAG Reset
Global Framer and BERT Reset
Global LIU Reset
Framer Receive Reset
Framer Transmit Reset
HDLC Receive Reset
HDLC Transmit Reset
Elastic Store Receive Reset
Elastic Store Transmit Reset
Bit Oriented Code Receive Reset
Loop Code Integration Reset
Spare Code Integration Reset
RESET FUNCTION
Resets and Power-Down Modes
LMCR
LMCR
register can be used to power down the LIU receiver.
T1RBOCC.7
T1RDNCD1,
T1RUPCD1
LOCATION
GFSRR.0:7
GLSRR.0:7
T1RSCD1
RESCR.2
TESCR.2
RMMR.1
TMMR.1
RESETB
THC1.5
RHC.6
JTRST
register can be used to disable the TTIP and TRING outputs and place
Transition to a logic 0 level resets the DS26528.
Resets the JTAG test port.
Writing to these bits resets the framer and BERT (transmit
and receive).
Writing to these bits resets the associated LIU.
Writing to this bit resets the receive framer.
Writing to this bit resets the transmit framer.
Writing to this bit resets the receive HDLC controller.
Writing to this bit resets the transmit HDLC controller.
Writing to this bit resets the receive elastic store.
Writing to this bit resets the transmit elastic store.
Writing to this bit resets the receive BOC controller.
Writing to these registers resets the programmable in-band
code integration period.
Writing to this register resets the programmable in-band
code integration period.
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COMMENTS
DS26528 Octal T1/E1/J1 Transceiver