MT41J64M16JT-15E:G Micron Technology Inc, MT41J64M16JT-15E:G Datasheet - Page 84

• Manufacturer Part Number: MT41J64M16JT-15E:G
• Description: MICMT41J64M16JT-15E:G DDR3 SDRAM 64MB X1
• Manufacturer: Micron Technology Inc
• Series: -r
• Type: DDR3 SDRAMr

Specifications of MT41J64M16JT-15E:G

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 96-TFBGA
• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 355mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Data Setup, Hold, and Derating
Table 58:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. F 11/08 EN
t
t
t
t
DH AC175 (base)
DH AC150 (base)
DS AC175 (base)
DS AC150 (base)
Symbol
Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based
DDR3-800
150
75
–
–
The total
sheet
page 67) to the Δ
Example:
signal has to remain above/below V
page 86).
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V
tion), a valid input signal is still required to complete the transition and to reach V
V
derating values may obtained by linear interpolation.
Setup (
last crossing of V
rate for a falling signal is defined as the slew rate between the last crossing of V
and the first crossing of V
nominal slew rate line between the shaded “V
slew rate for derating value (see Figure 39 on page 87). If the actual signal is later than the
nominal slew rate line anywhere between the shaded “V
rate of a tangent line to the actual signal from the AC level to the DC level is used for
derating value (see Figure 41 on page 89).
Hold (
last crossing of V
rate for a falling signal is defined as the slew rate between the last crossing of
V
nominal slew rate line between the shaded “DC-to-V
slew rate for derating value (see Figure 40 on page 88). If the actual signal is earlier than
the nominal slew rate line anywhere between the shaded “DC-to-V
slew rate of a tangent line to the actual signal from the “DC-to-V
for derating value (see Figure 42 on page 90).
IL
IH
(
(
AC
DC
t
). For slew rates which fall between the values listed in Table 59 on page 85, the
t
DS (base) and
DH) nominal slew rate for a rising signal is defined as the slew rate between the
) MIN and the first crossing of V
t
DS) nominal slew rate for a rising signal is defined as the slew rate between the
DDR3-1066
t
t
DS (setup time) and
DS (total setup time) =
100
25
–
–
t
REF
IL
DS and Δ
(
DC
(
DC
t
DH (base) values (see Table 58; values come from Table 53 on
) MAX and the first crossing of V
) and the first crossing of V
DDR3-1333
IL
t
DH derating values (see Table 59 on page 85), respectively.
(
AC
30
65
–
–
84
) MAX. If the actual signal is always earlier than the
t
DH (hold time) required is calculated by adding the data
t
DS (base) + Δ
IH
IH
(
[
REF
AC
AC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR3-1600
)/V
]/V
(
DC
45
10
IL
IL
–
–
). If the actual signal is always later than the
(
[
REF
AC
AC
t
DS. For a valid transition, the input
1Gb: x4, x8, x16 DDR3 SDRAM
) for some time
]) at the time of the rising clock transi-
(
DC
IH
(
)-to-AC region,” use the nominal
REF
AC
REF
) MIN. Setup (
(
REF
DC
(
Units
DC
ps
ps
ps
ps
(
) region,” use the nominal
DC
). Hold (
©2006 Micron Technology, Inc. All rights reserved.
)-to-AC region,” the slew
REF
t
VAC (see Table 61 on
Speed Bin Tables
REF
(
DC
t
DH) nominal slew
t
DS) nominal slew
(
) region” is used
V
V
V
V
DC
IH
IH
IH
IH
Reference
) region,” the
(
(
(
(
AC
DC
AC
DC
)/V
)/V
)/V
)/V
REF
IL
IL
IL
IL
(
(
(
(
AC
DC
AC
DC
(
IH
DC
)
)
)
)
/
)