MT41J64M16JT-15E:G Micron Technology Inc, MT41J64M16JT-15E:G Datasheet - Page 20

• Manufacturer Part Number: MT41J64M16JT-15E:G
• Description: MICMT41J64M16JT-15E:G DDR3 SDRAM 64MB X1
• Manufacturer: Micron Technology Inc
• Series: -r
• Type: DDR3 SDRAMr

Specifications of MT41J64M16JT-15E:G

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 96-TFBGA
• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 355mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 4:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
D1, D8, E1, G8, J2, J8,
J1, J9, L1, L9, M7, T7,
Ball Assignments
A1, A3, A7, A9, D3,
D2, D9, G7, K2, K8,
M1, M9, P1, P9, T1,
D7, G2, H3, H7, H8
E2, E8, F9, G1, G9
W1, W3, W7, W9
N1, N9, R1, R9
E9, F1, H2, H9
F8, H3, H8,
E3, F7, F2,
G2, H7
E3, F7,
E7, D7
F3, G3
F2, F8
M8
H1
T2
T9
L8
86-Ball FBGA – x4, x8 Ball Descriptions (continued)
DQ0, DQ1, DQ2,
DQ3, DQ4, DQ5,
TDQS, TDQS#
DQS, DQS#
DQ0, DQ1,
DQ2, DQ3
DQ6, DQ7
Symbol
V
RESET#
V
V
REF
V
REF
V
V
ZQ
NC
DD
NF
SS
DD
SS
DQ
CA
Q
Q
Reference External reference ball for output drive calibration: This ball is
Output
Supply
Supply
Supply
Supply
Supply
Supply
Input
Type
I/O
I/O
I/O
–
–
Description
Reset: RESET# is an active LOW CMOS input referenced to V
RESET# input receiver is a CMOS input defined as a rail-to-rail signal
with DC HIGH ≥ 0.8 × V
assertion and desertion are asynchronous.
Data input/output: Bidirectional data bus for the x4 configuration.
DQ[3:0] are referenced to V
Data input/output: Bidirectional data bus for the x8 configuration.
DQ[7:0] are referenced to V
Data strobe: Output with read data. Edge-aligned with read data.
Input with write data. Center-aligned to write data.
Termination data strobe: Applies to the x8 configuration only.
When TDQS is enabled, DM is disabled, and the TDQS and TDQS#
balls provide termination resistance.
Power supply: 1.5V ±0.075V.
DQ power supply: 1.5V ±0.075V. Isolated on the device for
improved noise immunity.
Reference voltage for control, command, and address: V
must be maintained at all times (including self refresh) for proper
device operation.
Reference voltage for data: V
times (including self refresh) for proper device operation.
Ground.
DQ ground: Isolated on the device for improved noise immunity.
tied to an external 240Ω resistor (RZQ), which is tied to V
No connect: These balls should be left unconnected (the ball has no
connection to the DRAM or to other balls).
No function: When configured as a x4 device, these balls are NF.
When configured as a x8 device, these balls are defined as TDQS#,
DQ[7:4].
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
DD
Q and DC LOW ≤ 0.2 × V
1Gb: x4, x8, x16 DDR3 SDRAM
REF
REF
DQ.
DQ.
REF
DQ must be maintained at all
©2006 Micron Technology, Inc. All rights reserved.
DD
Q. RESET#
SS
Q.
SS
. The
REF
CA