STK14D88-N25I Cypress Semiconductor Corp, STK14D88-N25I Datasheet - Page 13

• Manufacturer Part Number: STK14D88-N25I
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK14D88-N25I

• Word Size: 8b
• Organization: 32Kx8
• Density: 256Kb
• Interface Type: Parallel
• Access Time (max): 25ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: SOIC
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: -40C to 85C
• Pin Count: 32
• Mounting: Surface Mount
• Supply Current: 70mA
• Lead Free Status / Rohs Status: Not Compliant

To initiate the software STORE cycle, the following READ
sequence must be performed:
After the sixth address in the sequence has been entered, the
STORE cycle begins and the chip is disabled. It is important that
READ cycles and not WRITE cycles be used in the sequence.
After the t
activated for READ and WRITE operation.
Software RECALL
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL
cycle is initiated with a sequence of READ operations in a
manner similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of E controlled READ
operations must be performed:
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is trans-
ferred into the SRAM cells. After the t
SRAM will once again be ready for READ or WRITE operations.
The RECALL operation in no way alters the data in the nonvol-
atile storage elements.
Data Protection
The STK14D88 protects data from corruption during low-voltage
conditions by inhibiting all externally initiated STORE and
WRITE operations. The low-voltage condition is detected when
V
If the STK14D88 is in a WRITE mode (both E and W low) at
power up, after a RECALL, or after a STORE, the WRITE will be
inhibited until a negative transition on E or W is detected. This
protects against inadvertent writes during power up or brown out
conditions.
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
Document Number: 001-52037 Rev. *A
1. Read Address 0x0E38, Valid READ
2. Read Address 0x31C7, Valid READ
3. Read Address 0x03E0, Valid READ
4. Read Address 0x3C1F, Valid READ
5. Read Address 0x303F, Valid READ
6. Read Address 0x0FC0, Initiate STORE Cycle
1. Read Address 0x0E38, Valid READ
2. Read Address 0x31C7, Valid READ
3. Read Address 0x03E0, Valid READ
4. Read Address 0x3C1F, Valid READ
5. Read Address 0x303F, Valid READ
6. Read Address 0x0C63, Initiate RECALL Cycle
CC
<V
SWITCH
STORE
.
cycle time has been fulfilled, the SRAM is again
RECALL
cycle time, the
■
■
■
■
Low Average Active Power
CMOS technology provides the STK14D88 with the benefit of
power supply current that scales with cycle time. Less current will
be drawn as the memory cycle time becomes longer than 50 ns.
Figure 13
READ/WRITE cycle time. Worst-case current consumption is
shown for commercial temperature range, V
enable at maximum frequency. Only standby current is drawn
when the chip is disabled. The overall average current drawn by
the STK14D88 depends on the following items:
■
■
■
■
■
■
The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on, should always program a unique
NV pattern (for example, a complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
Power up boot firmware routines should rewrite the nvSRAM
into the desired state (such as AutoStore enabled). While the
nvSRAM is shipped in a preset state, best practice is to rewrite
the nvSRAM into the desired state as a safeguard against
events that might flip the bit inadvertently (such as program
bugs, incoming inspection routines, and others).
If AutoStore has been firmware disabled, it will not reset to
“autostore enabled” on every power down event captured by
the nvSRAM. The application firmware should re-enable or
re-disable AutoStore on each reset sequence based on the
behavior desired.
The V
and a maximum value size. Best practice is to meet this
requirement and not exceed the max V
nvSRAM internal algorithm calculates V
on this max V
V
time should discuss their V
understand any impact on the V
a t
The duty cycle of chip enable
The overall cycle rate for operations
The ratio of READs to WRITEs
The operating temperature
The V
I/O loading
CAP
RECALL
CAP
value to make sure there is extra store charge and store
CC
level
value specified in this data sheet includes a minimum
period.
shows
CAP
value. Customers who want to use a larger
the
relationship
CAP
size selection with Cypress to
CAP
voltage level at the end of
CAP
CAP
between
CC
value because the
charge time based
STK14D88
= 3.6V, and chip
Page 13 of 18
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CC
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