M25PX64-VMF6P NUMONYX, M25PX64-VMF6P Datasheet - Page 40

• Manufacturer Part Number: M25PX64-VMF6P
• Description: 64MB NOR FLASH
• Manufacturer: NUMONYX

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Read OTP (ROTP)
The device is first selected by driving Chip Select (S) Low. The instruction code for the read
OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte. Each
bit is latched in on the rising edge of Serial Clock (C).
Then the memory contents at that address are shifted out on serial data output (DQ1). Each
bit is shifted out at the maximum frequency, f
The instruction sequence is shown in
The address is automatically incremented to the next higher address after each byte of data
is shifted out.
There is no rollover mechanism with the read OTP (ROTP) instruction. This means that the
read OTP (ROTP) instruction must be sent with a maximum of 65 bytes to read, since once
the 65th byte has been read, the same (65th) byte keeps being read on the DQ1 pin.
The read OTP (ROTP) instruction is terminated by driving Chip Select (S) High. Chip Select
(S) can be driven High at any time during data output. Any read OTP (ROTP) instruction
issued while an erase, program or write cycle is in progress, is rejected without having any
effect on the cycle that is in progress.
Figure 18. Read OTP (ROTP) instruction and data-out sequence
1. A23 to A7 are don't care.
2. 1 ≤ n ≤ 65.
DQ0
DQ1
DQ0
DQ1
C
S
S
C
7
32 33 34
0
6
1
High Impedance
Dummy byte
5
2
Instruction
4
35
3
3
36 37 38 39 40 41 42 43 44 45 46
4
2
5
1
6
0
MSB
7
7
23
8
Figure
6
22 21
9 10
DATA OUT 1
5
24-bit address
4
C
18.
max, on the falling edge of Serial Clock (C).
3
3
28 29 30 31
2
2
1
1
0
47
0
MSB
7
6
DATA OUT n
5
4
3
2
1
0
MSB
AI13573
7