STM32W108CBU61TR STMicroelectronics, STM32W108CBU61TR Datasheet - Page 70
STM32W108CBU61TR
Manufacturer Part Number
STM32W108CBU61TR
Description
16/32-BITS MICROS
Manufacturer
STMicroelectronics
Series
STM32r
Specifications of STM32W108CBU61TR
Applications
RF4CE, Remote Control
Core Processor
ARM® Cortex-M3™
Program Memory Type
FLASH (128 kB)
Controller Series
STM32W
Ram Size
8K x 8
Interface
I²C, SPI, UART/USART
Number Of I /o
24
Voltage - Supply
1.18 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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General-purpose input/outputs
8.5.12
8.5.13
70/209
15
31
15
31
14
30
14
30
GPIO debug configuration register (GPIO_DBGCFG)
Address offset: 0xBC00
Reset value:
GPIO debug status register (GPIO_DBGSTAT)
Address offset: 0xBC04
Reset value:
Bit 3 INT_IRQDFLAG: IRQD interrupt pending.
Bit 2 INT_IRQCFLAG: IRQC interrupt pending.
Bit 1 INT_IRQBFLAG: IRQB interrupt pending.
Bit 0 INT_IRQAFLAG: IRQA interrupt pending.
Bit 5 GPIO_DEBUGDIS: Disable debug interface override of normal GPIO configuration.
Bit 4 GPIO_EXTREGEN: : Disable REG_EN override of PA7's normal GPIO configuration.
Bit 3 Reserved: this bit can change during normal operation. When writing to GPIO_DBGCFG, the
13
29
13
29
0: Permit debug interface to be active.
1: Disable debug interface (if it is not already active).
0: Enable override.
1: Disable override.
value of this bit must be preserved.
12
28
12
28
11
27
11
27
Reserved
0x0000 0010
0x0000 0000
10
26
10
26
Reserved
25
25
9
9
Doc ID 16252 Rev 8
24
24
8
8
Reserved
Reserved
23
23
7
7
22
22
6
6
DEBUG
GPIO_
DIS
21
rw
21
5
5
STM32W108CB, STM32W108HB
REGE
GPIO
_EXT
20
rw
20
N
4
4
QDFLA
INT_IR
rw
19
19
G
3
3
QCFLA
INT_IR
18
18
rw
G
2
2
Re-served
QBFLA
INT_IR
17
17
rw
G
1
1
QAFLA
INT_IR
rw
16
16
G
0
0
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