STM32W108CBU61TR STMicroelectronics, STM32W108CBU61TR Datasheet - Page 136
STM32W108CBU61TR
Manufacturer Part Number
STM32W108CBU61TR
Description
16/32-BITS MICROS
Manufacturer
STMicroelectronics
Series
STM32r
Specifications of STM32W108CBU61TR
Applications
RF4CE, Remote Control
Core Processor
ARM® Cortex-M3™
Program Memory Type
FLASH (128 kB)
Controller Series
STM32W
Ram Size
8K x 8
Interface
I²C, SPI, UART/USART
Number Of I /o
24
Voltage - Supply
1.18 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Figure 47. Triggering timer 2 with update of Timer 1
As in the previous example, both counters can be initialized before starting counting.
Figure 46
mode instead of gated mode (TIM_SMS = 110 in the TIM2_SMCR register).
Figure 48. Triggering Timer 2 with enable of Timer 1
Starting both timers synchronously in response to an external trigger
This example, sets the enable of Timer 1 when its TI1 input rises, and the enable of Timer 2
with the enable of Timer 1. Refer to
aligned, Timer 1 must be configured in master/slave mode (slave with respect to TI1, master
with respect to Timer 2):
●
●
●
Configure Timer 1 in master mode to send its Enable as trigger output (TIM_MMS =
001 in the TIM1_CR2 register).
Configure Timer 1 slave mode to get the input trigger from TI1 (TIM_TS = 100 in the
TIM1_SMCR register).
Configure Timer 1 in trigger mode (TIM_SMS = 110 in the TIM1_SMCR register).
shows the behavior with the same configuration shown in
Doc ID 16252 Rev 8
Figure 44
for connections. To ensure the counters are
STM32W108CB, STM32W108HB
Figure
47, but in trigger
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