PIC32MX675F512L-80V/PT Microchip Technology, PIC32MX675F512L-80V/PT Datasheet - Page 51
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PIC32MX675F512L-80V/PT
Manufacturer Part Number
PIC32MX675F512L-80V/PT
Description
512 KB Flash, 64 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 100 TQFP 12x
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80VPT.pdf
(256 pages)
Specifications of PIC32MX675F512L-80V/PT
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F512L-80V/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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TABLE 3-1:
The MIPS architecture defines that the result of a
multiply or divide operation be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and Move-
From-LO (MFLO) instructions, these values can be
transferred to the General Purpose Register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction,
MUL, which places the least significant results in the pri-
mary register file instead of the HI/LO register pair. By
avoiding the explicit MFLO instruction required when
using the LO register, and by supporting multiple desti-
nation registers, the throughput of multiply-intensive
operations is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
© 2009-2011 Microchip Technology Inc.
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU
MUL
DIV/DIVU
Opcode
MIPS
LATENCIES AND REPEAT RATES
®
M4K
®
CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT
Operand Size (mul rt) (div rs)
16 bits
32 bits
16 bits
32 bits
16 bits
24 bits
32 bits
8 bits
3.2.3
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (Kernel, User and Debug) and
whether interrupts are enabled or disabled. Configura-
tion information, such as presence of options like
MIPS16e, is also available by accessing the CP0
registers, listed in
PIC32MX5XX/6XX/7XX
SYSTEM CONTROL
COPROCESSOR (CP0)
Table
Latency
12
19
26
33
1
2
2
3
3-2.
DS61156G-page 51
Repeat Rate
18
25
32
11
1
2
1
2
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