PIC32MX675F512L-80V/PT Microchip Technology, PIC32MX675F512L-80V/PT Datasheet - Page 107
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PIC32MX675F512L-80V/PT
Manufacturer Part Number
PIC32MX675F512L-80V/PT
Description
512 KB Flash, 64 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 100 TQFP 12x
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80VPT.pdf
(256 pages)
Specifications of PIC32MX675F512L-80V/PT
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F512L-80V/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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- Download datasheet (6Mb)
TABLE 4-44:
Legend:
Note
5040
5050
5060 U1OTGSTAT
5070
5080
5200
5210
5220
5230
5240
5250
5260
5270
5280
U1OTGCON
U1OTGIR
1:
2:
3:
4:
U1FRML
U1STAT
U1OTGIE
U1BDTP1
U1PWRC
U1ADDR
U1EIR
U1CON
U1IR
U1EIE
U1IE
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See
more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET and INV registers.
Reset value for this bit is undefined.
(2)
(2)
(3)
(3)
(2)
(3)
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
USB REGISTER MAP
31/15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
28/12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
26/10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
24/8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UACTPND
DPPULUP
JSTATE
STALLIF
STALLIE
LSPDEN
BTSEF
BTSEE
23/7
IDIE
IDIF
Bits
—
—
—
ID
—
—
—
—
—
—
—
—
—
—
—
(4)
(4)
T1MSECIF LSTATEIF
T1MSECIE LSTATEIE
DMPULUP DPPULDWN DMPULDWN VBUSON
ATTACHIF RESUMEIF
ATTACHIE RESUMEIE
BMXEE
BMXEF
SE0
22/6
ENDPT<3:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(4)
TOKBUSY
LSTATE
DMAEE
PKTDIS
DMAEF
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(4)
BDTPTRL<7:1>
USLPGRD USBBUSY
USBRST
ACTVIF
ACTVIE
BTOEF
BTOEE
IDLEIF
IDLEIE
20/4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FRML<7:0>
DEVADDR<6:0>
SESVDIF SESENDIF
SESVDIE SESENDIE
DFN8EE
HOSTEN
DFN8EF
SESVD
TRNIE
TRNIF
19/3
DIR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
CRC16EF
CRC16EE
SESEND
RESUME
OTGEN
SOFIF
SOFIE
PPBI
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
USUSPEND USBPWR
VBUSCHG
CRC5EF
CRC5EE
PPBRST
UERRIF
UERRIE
EOFEF
EOFEE
17/1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VBUSVDIF 0000
VBUSVDIE 0000
DETACHIE 0000
DETACHIF 0000
VBUSDIS
VBUSVD
URSTIF
URSTIE
USBEN
SOFEN
PIDEF
PIDEE
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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