PIC32MX460F512LT-80V/BG Microchip Technology, PIC32MX460F512LT-80V/BG Datasheet - Page 95

• Manufacturer Part Number: PIC32MX460F512LT-80V/BG
• Description: 512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x10x1.20mm
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512LT-80V/BG

• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: XBGA-121
• Operating Temperature Range: - 40 C to + 105 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: -
• Eeprom Size: -
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

9.0
FIGURE 9-1:
© 2011 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
CTRL
2: Some registers and associated bits
PREFETCH CACHE
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
Cache” (DS61119) of the “PIC32 Family
Reference Manual”, which is available
from
(www.microchip.com/PIC32).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
Prefetch Control
Cache Control
Bus Control
Miss LRU
Hit LRU
the
FSM
PREFETCH MODULE BLOCK DIAGRAM
CTRL
Microchip
Tag Logic
Hit Logic
Prefetch
web
PFM
site
in
Address
Encode
Cache
Line
CTRL
Prefetch cache increases performance for applications
executing out of the cacheable program Flash memory
regions by implementing instruction caching, constant
data caching and instruction prefetching.
9.1
• 16 Fully Associative Lockable Cache Lines
• 16-byte Cache Lines
• Up to four Cache Lines Allocated to Data
• Two Cache Lines with Address Mask to hold
• Pseudo LRU replacement policy
• All Cache Lines are software writable
• 16-byte parallel memory fetch
• Predictive Instruction Prefetch
repeated instructions
Cache Line
PIC32MX3XX/4XX
Prefetch
Features
RDATA
RDATA
DS61143H-page 95