PIC32MX460F512LT-80V/BG Microchip Technology, PIC32MX460F512LT-80V/BG Datasheet - Page 37

• Manufacturer Part Number: PIC32MX460F512LT-80V/BG
• Description: 512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x10x1.20mm
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512LT-80V/BG

• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: XBGA-121
• Operating Temperature Range: - 40 C to + 105 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: -
• Eeprom Size: -
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

3.0
The MIPS32
PIC32MX3XX/4XX family processor. The CPU fetches
instructions, decodes each instruction, fetches source
operands, executes each instruction and writes the
results of instruction execution to the proper destina-
tions.
3.1
• 5-stage pipeline
• 32-bit Address and Data Paths
• MIPS32 Enhanced Architecture (Release 2)
FIGURE 3-1:
© 2011 Microchip Technology Inc.
- Multiply-Accumulate and Multiply-Subtract
- Targeted Multiply Instruction
- Zero/One Detect Instructions
- WAIT Instruction
- Conditional Move Instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
Note 1: This data sheet summarizes the features
Instructions
CPU
2: Some registers and associated bits
CPU
Features
of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 2. “CPU” (DS61113) of
the “PIC32 Family Reference Manual”,
which is available from the Microchip web
site
Resources for the MIPS32
Processor
www.mips.com/products/cores/
32-64-bit-cores/mips32-m4k/.
described in this section may not be avail-
able on all devices. Refer to
“Memory Organization”
sheet for device-specific register and bit
information.
®
M4K
the
®
Processor Core is the heart of the
PIC32MX3XX/4XX
MIPS
(RF/ALU/Shift)
Coprocessor
(www.microchip.com/PIC32).
Execution
Core
System
Core
MDU
®
M4K
are
®
BLOCK DIAGRAM
available
in this data
Section 4.0
family
®
FMT
M4K
at:
of
®
Bus Interface
• MIPS16e
• Simple Fixed Mapping Translation (FMT)
• Simple Dual Bus Interface
• Autonomous Multiply/Divide Unit
• Power Control
• EJTAG Debug and Instruction Trace
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
- Bit field manipulation instructions
- 16-bit encoding of 32-bit instructions to
- Special PC-relative instructions for efficient
- SAVE & RESTORE macro instructions for
- Improved support for handling 8 and 16-bit
mechanism
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
- Maximum issue rate of one 32x16 multiply
- Maximum issue rate of one 32x32 multiply
- Early-in iterative divide. Minimum 11 and
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
- Extensive use of local gated clocks
- Support for single stepping
- Virtual instruction and data address/value
- breakpoints
- PC tracing with trace compression
EJTAG
for interrupt handlers
improve code density
loading of addresses and constants
setting up and tearing down stack frames
within subroutines
data types
interrupt latency
per clock
every other clock
maximum 34 clock latency (dividend (rs) sign
extension-dependent)
instruction)
Mgmt.
Power
Trace
TAP
PIC32MX3XX/4XX
®
Code Compression
Dual Bus I/F
Debug I/F
Off-Chip
Trace I/F
DS61143H-page 37