MM912H634CM1AER2 Freescale Semiconductor, MM912H634CM1AER2 Datasheet - Page 94

• Manufacturer Part Number: MM912H634CM1AER2
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AER2

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Similarly, clock B is used as an input to an 8-bit down counter followed by a divide by two producing clock SB. Thus, clock SB
equals clock B divided by two times the value in the PWMSCLB register.
As an example, consider the case in which the user writes $FF into the PWMSCLA register. Clock A for this case will be E divided
by 4. A pulse will occur at a rate of once every 255x4 E cycles. Passing this through the divide by two circuit produces a clock
signal at an E divided by 2040 rate. Similarly, a value of $01 in the PWMSCLA register when clock A is E divided by 4 will produce
a clock at an E divided by 8 rate.
Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded. Otherwise, when changing rates
the counter would have to count down to $01 before counting at the proper rate. Forcing the associated counter to re-load the
scale register value every time PWMSCLA or PWMSCLB is written prevents this.
4.14.4.1.3
Each PWM channel has the capability of selecting one of two clocks. For channels 0 the clock choice is clock A or clock SA. For
channels 1 the choice is clock B or clock SB. The clock selection is done with the PCLKx control bits in the PWMCTL register.
4.14.4.2
The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register, and a duty
register (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the
counter. The duty is controlled by a match between the duty register and the counter value, and causes the state of the output to
change during the period. The starting polarity of the output is also selectable on a per channel basis. Shown in
block diagram for the PWM timer.
Freescale Semiconductor
PWM Channel Timers
Clock SA = Clock A / (2 * PWMSCLA)
When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A
is thus divided by 512.
Clock SB = Clock B / (2 * PWMSCLB)
When PWMSCLB = $00, PWMSCLB value is considered a full scale value of 256. Clock B
is thus divided by 512.
Writing to the scale registers while channels are operating can cause irregularities in the
PWM outputs.
Clock Select
Changing clock control bits while channels are operating can cause irregularities in the PWM
outputs.
MM912_634 Advance Information, Rev. 4.0
NOTE
NOTE
NOTE
NOTE
PWM Control Module (PWM8B2C)
Figure 24
is the
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