MM912H634CM1AER2 Freescale Semiconductor, MM912H634CM1AER2 Datasheet - Page 165

• Manufacturer Part Number: MM912H634CM1AER2
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AER2

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.29
4.29.1
The S12PMMC module controls the access to all internal memories and peripherals for the CPU12 and S12SBDM module. It
regulates access priorities and determines the address mapping of the on-chip resources.
the S12PMMC module.
4.29.1.1
4.29.1.2
The S12PMMC connects the CPU12’s and the S12SBDM’s bus interfaces to the MCU’s on-chip resources (memories and
peripherals). It arbitrates the bus accesses and determines all of the MCU’s memory maps. Furthermore, the S12PMMC is
responsible for constraining memory accesses on secured devices and for selecting the MCU’s functional mode.
4.29.1.3
The main features of this block are:
4.29.1.4
The S12PMMC selects the MCU’s functional mode. It also determines the devices behavior in secured and unsecured state.
4.29.1.4.1
Two functional modes are implements on devices of the S12I product family:
Freescale Semiconductor
Local Addresses
Global Address
Aligned Bus Access
Misaligned Bus Access
NS
SS
Unimplemented Address Ranges
P-Flash
D-Plash
NVM
IFR
•
•
•
•
•
•
•
•
Paging capability to support a global 256 kByte memory address space
Bus arbitration between the masters CPU12, S12SBDM to different resources.
MCU operation mode control
MCU security control
Separate memory map schemes for each master CPU12, S12SBDM
Generation of system reset when CPU12 accesses an unimplemented address (i.e., an address which does not belong
to any of the on-chip modules) in single-chip modes
Normal Single Chip (NS)
The mode used for running applications.
Special Single Chip Mode (SS)
A debug mode which causes the device to enter BDM Active Mode after each reset. Peripherals may also provide
special debug features in this mode.
Memory Map Control (S12PMMCV1)
Introduction
Glossary
Overview
Features
Modes of Operation
Functional Modes
Term
Address within the CPU12’s Local Address Map
Address within the Global Address Map
Bus access to an even address.
Bus access to an odd address.
Normal Single-chip Mode
Special Single-chip Mode
Address ranges which are not mapped to any on-chip resource.
Program Flash
Data Flash
Non-volatile Memory; P-Flash or D-Flash
NVM Information Row. Refer to FTMRC Block Guide
MM912_634 Advance Information, Rev. 4.0
Table 243. Glossary Of Terms
(Figure
Definition
52)
(Figure
Figure 47
52)
shows a block diagram of
165