MM912H634CM1AER2 Freescale Semiconductor, MM912H634CM1AER2 Datasheet - Page 125

• Manufacturer Part Number: MM912H634CM1AER2
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AER2

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Note:
4.19.3.3.7
116.
4.19.3.3.8
Freescale Semiconductor
Offset
Note:
117.
Offset
Reset
Reset
W
R
W
R
TOV[3-0]
TFFCA
(116)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Field
Field
(117)
TEN
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
3-0
7
4
0xC7
0xC8
OM3
7
0
0
Timer Enable
Timer Fast Flag Clear All
Toggle On Overflow Bits
7
0
Timer Toggle On Overflow Register 1 (TTOV)
TOVn toggles output compare pin on overflow. This feature only takes effect when the
corresponding channel is configured for an output compare mode. When set, an overflow
toggle on the output compare pin takes precedence over forced output compare events.
Timer Control Register 1 (TCTL1)
1 = Enables the timer.
0 = Disables the timer. (Used for reducing power consumption).
1 = For TFLG1 register, a read from an input capture or a write to the output compare channel [TC 3:0] causes the
corresponding channel flag, CnF, to be cleared.For TFLG2 register, any access to the TCNT register clears the TOF
flag. Any access to the PACNT registers clears the PAOVF and PAIF bits in the PAFLG register. This has the
advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental
flag clearing due to unintended accesses.
0 = Allows the timer flag clearing.
1 = Toggle output compare pin on overflow feature enabled.
0 = Toggle output compare pin on overflow feature disabled.
OL3
6
0
0
6
0
Table 174. Timer Toggle On Overflow Register 1 (TTOV)
Table 173. TSCR1 - Register Field Descriptions
Table 175. TTOV - Register Field Descriptions
Table 176. Timer Control Register 1 (TCTL1)
MM912_634 Advance Information, Rev. 4.0
OM2
5
0
0
5
0
OL2
NOTE
4
0
0
4
0
Description
Description
TOV3
OM1
3
0
3
0
Basic Timer Module - TIM (TIM16B4C)
TOV2
OL1
2
0
2
0
TOV1
OM0
1
0
Access: User read/write
1
0
Access: User read/write
TOV0
OL0
0
0
0
0
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