P89LPC936FDH-T NXP Semiconductors, P89LPC936FDH-T Datasheet - Page 62

• Manufacturer Part Number: P89LPC936FDH-T
• Description: MCU 8-Bit 89LP 80C51 CISC 16KB Flash 2.5V/3.3V 28-Pin TSSOP T/R
• Manufacturer: NXP Semiconductors

Specifications of P89LPC936FDH-T

• Package: 28TSSOP
• Device Core: 80C51
• Family Name: 89LP
• Maximum Speed: 18 MHz
• Ram Size: 768 Byte
• Program Memory Size: 16 KB
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 26
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx8-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 2

NXP Semiconductors
Table 13.
V
T
P89LPC933_934_935_936
Product data sheet
Symbol
f
f
f
T
f
Glitch filter
t
t
External clock
t
t
t
t
Shift register (UART mode 0)
T
t
t
t
t
SPI interface
f
T
t
t
osc(RC)
osc(WD)
osc
CLKLP
gr
sa
CHCX
CLCX
CLCH
CHCL
QVXH
XHQX
XHDX
XHDV
SPI
SPILEAD
SPILAG
amb
DD
cy(CLK)
XLXL
SPICYC
= 3.0 V to 3.6 V unless otherwise specified.
= −40 °C to +85 °C for industrial, −40 °C to +125 °C for extended, unless otherwise specified.
Dynamic characteristics (18 MHz)
Parameter
internal RC oscillator frequency
internal watchdog oscillator
frequency
oscillator frequency
clock cycle
low-power select clock
frequency
glitch rejection time
signal acceptance time
clock HIGH time
clock LOW time
clock rise time
clock fall time
serial port clock cycle time
output data set-up to clock
rising edge time
output data hold after clock
rising edge time
input data hold after clock rising
edge time
input data valid to clock rising
edge time
SPI operating frequency
SPI cycle time
SPI enable lead time
SPI enable lag time
slave
master
slave
master
slave
slave
All information provided in this document is subject to legal disclaimers.
Conditions
see
P1.5/RST pin
any pin except
P1.5/RST
P1.5/RST pin
any pin except
P1.5/RST
see
see
see
see
see
see
see
see
see
see
29,
see
see
30
Rev. 8 — 12 January 2011
Figure 27
Figure 27
Figure 27
Figure 27
Figure 27
Figure 25
Figure 25
Figure 25
Figure 25
Figure 25
Figure
Figure
Figure
8-bit microcontroller with accelerated two-clock 80C51 core
26, 28,
29,
29,
30
30
P89LPC933/934/935/936
16T
13T
7.189
6
4
Min
320
125
150
⁄
⁄
250
250
CCLK
CCLK
55
50
22
22
cy(CLK)
cy(CLK)
0
0
0
-
-
-
-
-
-
-
Variable clock
T
T
cy(CLK)
T
cy(CLK)
cy(CLK)
7.557
CCLK
CCLK
Max
520
18
50
15
8
5
5
0
-
-
-
-
-
-
-
-
-
-
− t
− t
⁄
⁄
+ 20
6
4
CHCX
CLCX
[1][2]
f
7.189
osc
Min
320
125
888
722
150
333
222
250
250
50
22
22
0
© NXP B.V. 2011. All rights reserved.
-
-
-
-
-
-
-
-
-
-
= 18 MHz Unit
7.557 MHz
Max
520
3.0
4.5
50
15
75
5
5
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
62 of 77
kHz
MHz
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns