GS832036T-250I GSI TECHNOLOGY, GS832036T-250I Datasheet

GS832036T-250I

Manufacturer Part Number

GS832036T-250I

Description

Manufacturer

GSI TECHNOLOGY

Datasheet

1.GS832036T-250I.pdf (25 pages)

Specifications of GS832036T-250I

Density

36Mb

Access Time (max)

6.5ns

Sync/async

Synchronous

Architecture

SDR

Clock Freq (max)

153MHz

Operating Supply Voltage (typ)

2.5/3.3V

Address Bus

20b

Package Type

TQFP

Operating Temp Range

-40C to 85C

Number Of Ports

Supply Current

210mA

Operating Supply Voltage (min)

2.3/3V

Operating Supply Voltage (max)

2.7/3.6V

Operating Temperature Classification

Industrial

Mounting

Surface Mount

Pin Count

100

Word Size

36b

Number Of Words

Lead Free Status / Rohs Status

Not Compliant

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline

• Single Cycle Deselect (SCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

Applications

The GS832018/32/36T is a 37,748,736-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

Rev: 1.03b 12/2007

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

operation

Through

Pipeline

3-1-1-1

2-1-1-1

Flow

2M x 18, 1M x 32, 1M x 36

36Mb Sync Burst SRAMs

Curr

tCycle

(x32/x36)

(x18)

Parameter Synopsis

1/25

-250 -225 -200 -166 -150 -133 Unit

285

350

205

235

2.5

4.0

6.5

265

320

195

225

2.7

4.4

7.0

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS832018/32/36T operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

from the internal circuits and are 3.3 V and 2.5 V compatible.

245

295

185

210

3.0

5.0

7.5

GS832018/32/36T-250/225/200/166/150/133

220

260

175

200

3.5

6.0

8.0

210

240

165

190

3.8

6.6

8.5

DDQ

185

215

155

175

4.0

7.5

8.5

) pins are used to decouple output noise

250 MHz–133 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS832036T-250I

GS832036T-250I Summary of contents

Page 1

... Curr 205 195 185 175 165 (x18) Curr 235 225 210 200 190 (x32/x36) 1/25 250 MHz–133 MHz 3.3 V I/O ) pins are used to decouple output noise DDQ 4.0 ns 7.5 ns 185 mA 215 mA 8.5 ns 8.5 ns 155 mA 175 mA © 2003, GSI Technology DD ...

Page 2

... DDQ DDQ DDQ DQP DDQ Rev: 1.03b 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 GS832018 100-Pin TQFP Pinout Top View 2/ DDQ DQP DDQ DDQ DDQ © 2003, GSI Technology ...

Page 3

... DDQ DDQ DDQ DDQ Rev: 1.03b 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 GS832032 100-Pin TQFP Pinout Top View 3/ DDQ DDQ DDQ DDQ © 2003, GSI Technology ...

Page 4

... V 4 DDQ DDQ DDQ DDQ DQP Rev: 1.03b 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 GS832036 100-Pin TQFP Pinout Top View 4/25 DQP DDQ DDQ DDQ DDQ DQP 51 A © 2003, GSI Technology ...

Page 5

... Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply 5/25 © 2003, GSI Technology ...

Page 6

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 GS832018/32/36 Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 6/25 A Memory Array – DQx1 DQx9 © 2003, GSI Technology ...

Page 7

... Interleaved Burst Flow Through Pipeline Active Standby Dual Cycle Deselect Single Cycle Deselect High Drive (Low Impedance) Low Drive (High Impedance) Activate DQPx I/Os (x18/x3672 mode) Deactivate DQPx I/Os (x16/x3272 mode) A[1:0] A[1:0] A[1:0] A[1: BPR 1999.05.18 © 2003, GSI Technology ...

Page 8

... C D Rev: 1.03b 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 may be used in any combination with BW to write single or multiple bytes Notes © 2003, GSI Technology ...

Page 9

... Rev: 1.03b 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 State Diagram Key None X H None X L None Next CR X Next CR H Next CW X Next 9/25 2 ADSP ADSC ADV © 2003, GSI Technology High-Z X High-Z X High ...

Page 10

... ADSP is tied high and ADV is tied low. Rev: 1.03b 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 Simplified State Diagram X Deselect First Write Burst Write CR CW 10/ First Read Burst Read BW, and GW © 2003, GSI Technology ...

Page 11

... Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.03b 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 Simplified State Diagram with G X Deselect First Write Burst Write 11/ First Read Burst Read CR © 2003, GSI Technology ...

Page 12

... Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 2003, GSI Technology Unit Notes ...

Page 13

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 13/25 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 2003, GSI Technology ...

Page 14

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 Overshoot Measurement and Timing Symbol Test conditions I/O OUT Conditions V – DDQ V /2 DDQ Fig. 1 Output Load 1 50Ω 30pF V DDQ/2 * Distributed Test Jig Capacitance 14/25 20% tKC DD IL Typ. Max. Unit © 2003, GSI Technology ...

Page 15

Page 16

Page 17

... GSI Technology -133 Unit Min Max 7.5 ns — — 4.0 ns 1.5 ns — 1.5 — ns 1.5 ns — 0.5 — ns 8.5 ns — — 8 ...

Page 18

... E2 and E3 only sampled with ADSP and ADSC tS tOHZ tH Q(A) D(B) 18/25 Read C+1 Read C+2 Read C+3 Cont Burst Read Burst Read Deselected with E1 E1 masks ADSP tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2003, GSI Technology Deselect tKQX tHZ ...

Page 19

... Flow Through Mode Timing Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read tKQ tOHZ tLZ D(B) Q(C) 19/25 Cont Deselect Deselected with E1 tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2003, GSI Technology tKQX ...

Page 20

... Hold ADSP ADSC ZZ Rev: 1.03b 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 Sleep Mode Timing Diagram tKH tKH tKC tKC tKL tKL tZZS tZZH 20/25 2. The duration of SB tZZR © 2003, GSI Technology ...

Page 21

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832018/32/36T-250/225/200/166/150/133 θ 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 21/ © 2003, GSI Technology ...

Page 22

... GS832018T-166 GS832018T-150 GS832018T-133 GS832032T-250 GS832032T-225 GS832032T-200 GS832032T-166 GS832032T-150 GS832032T-133 GS832036T-250 GS832036T-225 GS832036T-200 GS832036T-166 GS832036T-150 GS832036T-133 GS832018T-250I GS832018T-225I GS832018T-200I GS832018T-166I GS832018T-150I GS832018T-133I GS832032T-250I GS832032T-225I GS832032T-200I GS832032T-166I GS832032T-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832018T-150IT. ...

Page 23

... Ordering Information for GSI Synchronous Burst RAMs 1 Org Part Number GS832032T-133I GS832036T-250I GS832036T-225I GS832036T-200I GS832036T-166I GS832036T-150I GS832036T-133I GS832018GT-250 GS832018GT-225 GS832018GT-200 GS832018GT-166 GS832018GT-150 GS832018GT-133 GS832032GT-250 GS832032GT-225 GS832032GT-200 GS832032GT-166 GS832032GT-150 GS832032GT-133 GS832036GT-250 GS832036GT-225 GS832036GT-200 GS832036GT-166 GS832036GT-150 GS832036GT-133 GS832018GT-250I GS832018GT-225I GS832018GT-200I GS832018GT-166I GS832018GT-150I GS832018GT-133I Notes: 1 ...

Page 24

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.03b 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 25

... Updated format • Added RoHS-compliant information for TQFP package Content/Format • (Rev. 1.02b: Removed status column from ordering information table) • Updated format Content/Format • (Rev. 1.03b: Removed status column from ordering information table) 25/25 Page;Revisions;Reason © 2003, GSI Technology ...

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