JN5148/001,531 NXP Semiconductors, JN5148/001,531 Datasheet - Page 88

Microcontrollers (MCU) 32bit RISC 2.4GHz

JN5148/001,531

Manufacturer Part Number
JN5148/001,531
Description
Microcontrollers (MCU) 32bit RISC 2.4GHz
Manufacturer
NXP Semiconductors
Datasheet

Specifications of JN5148/001,531

Core
RISC
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-56
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
 Details
Appendix B Development Support
B.1 Crystal Oscillators
This section covers some of the general background to crystal oscillators, to help the user make informed decisions
concerning the choice of crystal and the associated capacitors.
B.1.1 Crystal Equivalent Circuit
Where
B.1.2 Crystal Load Capacitance
The crystal load capacitance is the total capacitance seen at the crystal pins, from all sources. As the load
capacitance (CL) affects the oscillation frequency by a process known as ‘pulling’, crystal manufacturers specify the
frequency for a given load capacitance only. A typical pulling coefficient is 15ppm/pF, to put this into context the
maximum frequency error in the IEEE802.15.4 specification is +/-40ppm for the transmitted signal. Therefore, it is
important for resonance at 32MHz exactly, that the specified load capacitance is provided.
The load capacitance can be calculated using:
Total capacitance
Where
Similarly for
Hence for a 9pF load capacitance, and a tight layout the external capacitors should be 15pF
88
C
C
C
C
C
L
R
m
m
m
S
1
1
1
P
in
C
is the motional inductance. This together with
is the motional capacitance
is the equivalent series resistance ( ESR ).
is the capacitor component
is the shunt or package capacitance and this is a parasitic
is the PCB parasitic capacitance. With the recommended layout this is about 1.6pF
T
is the on-chip parasitic capacitance and is about 1.4pF typically.
2
C1
Lm
JN-DS-JN5148-001 1v6
CL
C
T
1
=
=
Cs
C
Rm
C
C
1
C
+
T
T
1
1
m
C
×
+
defines the oscillation frequency (series)
1
C
C
P
T
T
+
2
2
C
Cm
1
C2
in
© NXP Laboratories UK 2010

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