JN5148/001,531 NXP Semiconductors, JN5148/001,531 Datasheet - Page 25

• Manufacturer Part Number: JN5148/001,531
• Description: Microcontrollers (MCU) 32bit RISC 2.4GHz
• Manufacturer: NXP Semiconductors

Specifications of JN5148/001,531

• Core: RISC
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-56
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Details

7.3 Hardware Interrupts
Hardware interrupts generated from the transceiver, analogue or digital peripherals and DIO pins are individually
masked using the Programmable Interrupt Controller (PIC). Management of interrupts is provided in the peripherals
library [5]. For details of the interrupts generated from each peripheral see the respective section in this datasheet.
Interrupts can be used to wake the JN5148 from sleep. The peripherals, baseband controller, security coprocessor
and PIC are powered down during sleep but the DIO interrupts and optionally the pulse counters, wake-up timers and
analogue comparator interrupts remain powered to bring the JN5148 out of sleep.
Prioritised external interrupt handling (i.e., interrupts from hardware peripherals) is provided to enable an application
to control an events priority to provide for deterministic program execution.
The priority Interrupt controller provides 15 levels of prioritised interrupts. The priority level of all interrupts can be set,
with value 0 being used to indicate that the source can never produce an external interrupt, 1 for the lowest priority
source(s) and 15 for the highest priority source(s). Note that multiple interrupt sources can be assigned the same
priority level if desired.
If while processing an interrupt, a new event occurs at the same or lower priority level, a new external interrupt will
not be triggered. However, if a new higher priority event occurs, the external interrupt will again be asserted,
interrupting the current interrupt service routine.
Once the interrupt service routine is complete, lower priority events can be serviced.
© NXP Laboratories UK 2010
JN-DS-JN5148-001 1v6
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