TLE7269G Infineon Technologies, TLE7269G Datasheet - Page 25

• Manufacturer Part Number: TLE7269G
• Description: IC TRANSCEIVER LIN DSO-14
• Manufacturer: Infineon Technologies
• Type: Transceiverr

Specifications of TLE7269G

• Number Of Drivers/receivers: 2/2
• Protocol: LIN
• Voltage - Supply: 7 V ~ 27 V
• Mounting Type: Surface Mount
• Package / Case: DSO-14
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SP000104277; TLE7269G; TLE7269GTR

Table 7
7.0 V < V
flowing into pin; unless otherwise specified.
Pos.
6.1.65 Duty cycle D1
6.1.66 Duty cycle D2
6.1.67 Duty cycle D3
6.1.68 Duty cycle D4
1) Not subject to production test, specified by design
2) Minimum limit specified by design
3) Maximum limit specified by design
4)
5)
6) Bus load concerning LIN Spec 2.1:
Data Sheet
V
V
Load 1 = 1 nF / 1 kΩ =
Load 2 = 6,8 nF / 660 Ω =
Load 3 = 10 nF / 500 Ω =
BUS_CNT
HYS
Parameter
(for worst case at 20 kBit/s)
(for worst case at 20 kBit/s)
(for worst case at 10.4 kBit/s)
Low Slope Mode
(for worst case at 10.4 kBit/s)
Low Slope Mode
= V
S
< 27 V; R
= (V
BUSrec
Electrical Characteristics (cont’d)
th_dom
- V
L
BUSdom
= 500 Ω; V
- V
C
th rec
BUS
C
C
)/2;
BUS
BUS
/
R
/
BUS
io
/
R
R
= 5V; -40 °C < T
BUS
BUS
Symbol
D1
D2
D3
D4
j
Limit Values
Min.
0.396
–
0.417
–
< 125 °C; all voltages with respect to ground; positive current
25
Typ.
–
–
–
–
Max.
–
0.581
–
0.590
Unit Remarks
–
–
–
–
duty cycle 1
TH
TH
V
t
D1 = t
LIN Spec 2.1 (Par. 27)
duty cycle 2
TH
TH
V
t
D2 = t
LIN Spec 2.1 (Par. 28)
duty cycle 3
TH
TH
V
t
D3 = t
LIN Spec 2.1 (Par. 29)
duty cycle 4
TH
TH
V
t
D4 = t
LIN Spec 2.1 (Par. 30)
bit
bit
bit
bit
S
S
S
S
Electrical Characteristics
= 50 µs;
= 50 µs;
= 96µs;
= 96µs;
Rec
Dom
Rec
Dom
Rec
Dom
Rec
Dom
= 7.0 … 18 V;
= 7.6 … 18 V;
= 7.0 … 18 V;
= 7.6 … 18 V;
(max) = 0.744 × V
(min)= 0.422 × V
(max) = 0.778 × V
(min) = 0.389 × V
bus_rec(min)
bus_rec(max)
bus_rec(min)
bus_rec(max)
(max) =0.581 × V
(min)= 0.284 × V
(max) =0.616 × V
(min) =0.251 × V
Rev. 1.2, 2007-11-13
6)
6)
6)
6)
/2 t
/2 t
TLE7269G
/2 t
/2 t
bit
bit
bit
bit
;
;
;
;
S
S
S
S;
;
S
S
S;
S;
;