PIC16LF1826-I/SS Microchip Technology Inc., PIC16LF1826-I/SS Datasheet - Page 89
PIC16LF1826-I/SS
Manufacturer Part Number
PIC16LF1826-I/SS
Description
3.5 KB Flash, 256 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, n
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F1826-ISO.pdf
(406 pages)
Specifications of PIC16LF1826-I/SS
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
8 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin SSOP
Programmable Memory
3.5K Bytes
Ram Size
256 Bytes
Speed
32 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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8.6.4
The PIE3 register contains the interrupt enable bits, as
shown in
REGISTER 8-4:
2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
—
Register
This register is only available on PIC16(L)F1827.
PIE3 REGISTER
Unimplemented: Read as ‘0’
CCP4IE: CCP4 Interrupt Enable bit
1 = Enables the CCP4 interrupt
0 = Disables the CCP4 interrupt
CCP3IE: CCP3 Interrupt Enable bit
1 = Enables the CCP3 interrupt
0 = Disables the CCP3 interrupt
TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1 = Enables the TMR6 to PR6 Match interrupt
0 = Disables the TMR6 to PR6 Match interrupt
Unimplemented: Read as ‘0’
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enables the TMR4 to PR4 Match interrupt
0 = Disables the TMR4 to PR4 Match interrupt
Unimplemented: Read as ‘0’
8-4.
U-0
—
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
CCP4IE
R/W-0/0
CCP3IE
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
TMR6IE
Note:
PIC16(L)F1826/27
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
U-0
—
(1)
R/W-0/0
TMR4IE
DS41391D-page 89
U-0
—
bit 0
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