PIC16LF1826-I/SS Microchip Technology Inc., PIC16LF1826-I/SS Datasheet - Page 47
PIC16LF1826-I/SS
Manufacturer Part Number
PIC16LF1826-I/SS
Description
3.5 KB Flash, 256 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, n
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F1826-ISO.pdf
(406 pages)
Specifications of PIC16LF1826-I/SS
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
8 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin SSOP
Programmable Memory
3.5K Bytes
Ram Size
256 Bytes
Speed
32 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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4.2
Code protection allows the device to be protected from
unauthorized access. Program memory protection and
data EEPROM protection are controlled independently.
Internal access to the program memory and data
EEPROM are unaffected by any code protection
setting.
4.2.1
The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Word 1. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection
Protection”
4.2.2
The entire data EEPROM is protected from external
reads and writes by the CPD bit. When CPD = 0, exter-
nal reads and writes of data EEPROM are inhibited.
The CPU can continue to read and write data EEPROM
regardless of the protection bit settings.
4.3
Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot-
loader software, can be protected while allowing other
regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Word 2 define the
size of the program memory block that is protected.
4.4
Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See
Section 11.5 “User ID, Device ID and Configuration
Word Access”
these memory locations. For more information on
checksum calculation, see the “PIC16F/LF1826/27
Memory Programming Specification” (DS41390).
2011 Microchip Technology Inc.
Code Protection
Write Protection
User ID
PROGRAM MEMORY PROTECTION
DATA EEPROM PROTECTION
for more information.
setting.
for more information on accessing
See
Section 4.3
“Write
PIC16(L)F1826/27
DS41391D-page 47
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