PIC16C505-04I/P Microchip Technology Inc., PIC16C505-04I/P Datasheet - Page 37

• Manufacturer Part Number: PIC16C505-04I/P
• Description: 14 PIN, 1.5 KB OTP, 72 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16C505-04I/P

• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 11
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 1.5K Bytes
• Ram Size: 72 Bytes
• Speed: 4 MHz
• Timers: 1- 8-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

7.9
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
7.9.1
The Power-Down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low or hi-impedance).
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR pin low.
For lowest current consumption while powered down,
the T0CKI input should be at V
MCLR/V
MCLR is enabled.
7.9.2
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
These events cause a device reset. The TO, PD, and
RBWUF bits can be used to determine the cause of
device reset. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEP is invoked.
The RBWUF bit indicates a change in state while in
SLEEP at pins RB0, RB1, RB3 or RB4 (since the last
file or bit operation on RB port).
The WDT is cleared when the device wakes from
sleep, regardless of the wake-up source.
Caution: Right before entering SLEEP, read the
1999 Microchip Technology Inc.
An external reset input on RB3/MCLR/V
when configured as MCLR.
A Watchdog Timer time-out reset (if WDT was
enabled).
A change on input pin RB0, RB1, RB3 or RB4
when wake-up on change is enabled.
PP
Power-Down Mode (SLEEP)
SLEEP
WAKE-UP FROM SLEEP
input pins. When in SLEEP, wake up
occurs when the values at the pins change
from the state they were in at the last
reading. If a wake-up on change occurs
and the pins are not read before reentering
SLEEP, a wake-up will occur immediately
even if no pins change while in SLEEP
mode.
pin must be at a logic high level (V
DD
or V
SS
and the RB3/
PP
IHMC
pin,
) if
7.10
If the code protection bit has not been programmed,
the on-chip program memory can be read out for
verification purposes.
The first 64 locations and the last location (OSCCAL)
can be read, regardless of the code protection bit
setting.
7.11
Four memory locations are designated as ID locations
where the user can store checksum or other code-
identification numbers. These locations are not
accessible during normal execution, but are readable
and writable during program/verify.
Use only the lower 4 bits of the ID locations and
always program the upper 8 bits as ’0’s.
Program Verification/Code Protection
ID Locations
PIC16C505
DS40192C-page 37