5962-9763101QXA Cypress Semiconductor Corp, 5962-9763101QXA Datasheet - Page 4

• Manufacturer Part Number: 5962-9763101QXA
• Manufacturer: Cypress Semiconductor Corp

Specifications of 5962-9763101QXA

• Lead Free Status / Rohs Status: Not Compliant

DSCC FORM 2234
APR 97
Unless otherwise specified, the issues of the documents which are DoD adopted are those listed in the issue of the DODISS
cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DODISS are the issues of the
documents cited in the solicitation.
1916 Race Street, Philadelphia, PA 19103.)
22201).
distribute the documents. These documents also may be available in or through libraries or other informational services.)
of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations unless
a specific exemption has been obtained.
38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in
the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M
shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein.
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
tests for each subgroup are defined in table I.
marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space
limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the
RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A.
in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 2.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required
JEDEC Standard No. 17
(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Blvd., Arlington, VA
(Non-Government standards and other publications are normally available from the organizations that prepare or
ASTM Standard F1192-88
(Applications for copies of ASTM publications should be addressed to the American Society for Testing and Materials,
ELECTRONICS INDUSTRIES ASSOCIATION (EIA)
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
MICROCIRCUIT DRAWING
STANDARD
-
-
Standard Guide for the Measurement of Single Event Phenomena from
Heavy Ion Irradiation of Semiconductor Devices.
Latch-up in CMOS Integrated Circuits.
A Standardized Test Procedure for the Characterization of
SIZE
A
REVISION LEVEL
SHEET
5962-97631
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