LPC2194HBD64/01-S NXP Semiconductors, LPC2194HBD64/01-S Datasheet - Page 22

• Manufacturer Part Number: LPC2194HBD64/01-S
• Description: MCU 16-Bit/32-Bit LPC2000 ARM7TDMI-S RISC 256KB Flash 1.8V/3.3V 64-Pin LQFP Tray
• Manufacturer: NXP Semiconductors

Specifications of LPC2194HBD64/01-S

• Package: 64LQFP
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 60 MHz
• Ram Size: 16 KB
• Program Memory Size: 256 KB
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 16|32 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 46
• Interface Type: CAN/I2C/SPI/SSP/UART
• On-chip Adc: 4-chx10-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 2

NXP Semiconductors
LPC2194_5
Product data sheet
6.19.1 EmbeddedICE
6.19.2 Embedded trace macrocell
6.19 Emulation and debugging
when an application does not require any peripherals to run at the full processor rate.
Because the APB divider is connected to the PLL output, the PLL remains active (if it was
running) during Idle mode.
The LPC2194 support emulation and debugging via a JTAG serial port. A trace port
allows tracing program execution. Debugging and trace functions are multiplexed only with
GPIOs on Port 1. This means that all communication, timer and interface peripherals
residing on Port 0 are available during the development and debugging phase as they are
when the application is run in the embedded system itself.
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote
Debug Protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a Debug Communication Channel function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or even
entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic.
The JTAG clock (TCK) must be slower than
interface to operate.
Since the LPC2194 have significant amounts of on-chip memory, it is not possible to
determine how the processor core is operating simply by observing the external pins. The
Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply
embedded processor cores. It outputs information about processor execution to the trace
port.
The ETM is connected directly to the ARM core and not to the main AMBA system bus. It
compresses the trace information and exports it through a narrow trace port. An external
trace port analyzer must capture the trace information under software debugger control.
Instruction trace (or PC trace) shows the flow of execution of the processor and provides a
list of all the instructions that were executed. Instruction trace is significantly compressed
by only broadcasting branch addresses as well as a set of status signals that indicate the
pipeline status on a cycle by cycle basis. Trace information generation can be controlled
by selecting the trigger resource. Trigger resources include address comparators,
counters and sequencers. Since trace information is compressed the software debugger
requires a static image of the code being executed. Self-modifying code can not be traced
because of this restriction.
Rev. 05 — 10 December 2007
1
6
of the CPU clock (CCLK) for the JTAG
Single-chip 16/32-bit microcontroller
LPC2194
© NXP B.V. 2007. All rights reserved.
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