PSF21150FV14XP Infineon Technologies, PSF21150FV14XP Datasheet - Page 48
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PSF21150FV14XP
Manufacturer Part Number
PSF21150FV14XP
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSF21150FV14XP.pdf
(270 pages)
Specifications of PSF21150FV14XP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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3.3
The layer-1 functions for the S/T interface of the IPAC-X are:
– Line transceiver functions for the S/T interface according to the electrical
– Conversion of the frame structure between IOM-2 and S/T interface;
– Conversion from/to binary to/from pseudo-ternary code;
– Level detection
– Receive timing recovery for point-topoint, passive bus and extended passive bus
– S/T timing generation using IOM-2 timing synchronous to system, or vice versa;
– D-channel access control and priority handling;
– D-channel echo bit generation by handling of the global echo bit;
– Activation/deactivation procedures, triggered by primitives received over the IOM-2
– Execution of test loops.
The wiring configurations in user premises, in which the IPAC-X can be used, are
illustrated in
Data Sheet
specifications of ITU-T I.430;
configuration
C/I channel or by INFO's received from the line;
S/T-Interface
Figure
18.
48
Description of Functional Blocks
PSB/PSF 21150
2003-01-30
IPAC-X
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