PSF21150FV14XP Infineon Technologies, PSF21150FV14XP Datasheet - Page 114
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
PSF21150FV14XP
Manufacturer Part Number
PSF21150FV14XP
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSF21150FV14XP.pdf
(270 pages)
Specifications of PSF21150FV14XP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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3.7.2.2
The strobed IOM-2 bit clock is active during the programmed window. Outside the
programmed window a ’0’ is driven. Two examples are shown in
Figure 64
The strobed bit clock can be enabled in SDS_CONF.SDS1/2_BCL.
Data Sheet
FSC
DD,DU
SDS1
(Example1)
SDS1
(Example2)
Example 1:
Example 2:
For all examples SDS_CONF.SDS1_BCL must be set to “1”.
Strobed IOM-2 Bit Clock
Strobed IOM-2 Bit Clock. Register SDS_CONF Programmed to 01
Setting of SDS1_CR:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
TS0
B1
TS1
B2
MON0
TS2
= '0
= '0'
= '0'
= '1'
= '5
= '1'
= '1'
= '0'
D CI0
H
H
TS3
'
'
M
R
M
X
TS4
IC1
TS5
IC2 MON1
114
TS6
CI1
TS7
Description of Functional Blocks
M
R
M
X
TS8
TS9
Figure
TS10
PSB/PSF 21150
TS11
64.
bcl_strobed.vsd
TS0
2003-01-30
IPAC-X
TS1
H
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