PEB24911HV13TR Lantiq, PEB24911HV13TR Datasheet - Page 147

• Manufacturer Part Number: PEB24911HV13TR
• Manufacturer: Lantiq

Specifications of PEB24911HV13TR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Parameter
Superframe FSC pulse width, high
DIN setup time
DIN hold time
Table 20
DCL Data delay clock
Pin PUP = ’0’
Pin PUP = ’1’
FSC Data delay frame
Notes:
7.4.3
The AC characteristics of the AFE-interface pins are optimized to fit to AFE Version 2.1
if the following loads are not exceeded.
Table 21
Pin
CL15
SDR
PDM0 3
SDX
Data Sheet
Parameter
1)
either FSC (
DCL) shall be the reference.
The point of time at which the output data will be valid is referred to the rising edges of
Interface to the Analog Front End
IOM
Interface Signals of AFE and DFE-Q
Signal Driving Device
AFE
AFE
AFE
DFE-Q
t
®
dDF
-2 Dynamic Output Characteristics
) or DCL (
1)
1)
Symbol Limit Values
t
t
t
dDC
dDC
dDF
t
dDC
). The rising edge of the signal appearing last (normally
Symbol Limit Values
t
t
t
min. typ.
wFH
sD
hD
137
Max. Capacitive Load
Max. Connection resistance
50pF; 2 Ohms
20pF; 2 Ohms
20pF; 2 Ohms
20pF; 2 Ohms
min.
100
10
10
max.
100
40
20
Unit Test Condition
ns
ns
ns
typ.
1
Electrical Characteristics
T
DCL
C
Charged with 5V
C
Charged with 3.3V
C
L
L
L
= 150 pF,
= 100 pF,
= 150 pF
max.
PEF 24911
2001-07-16
Unit
ns
ns
ns