PEB3086FV14XT Lantiq, PEB3086FV14XT Datasheet - Page 226

• Manufacturer Part Number: PEB3086FV14XT
• Manufacturer: Lantiq

Specifications of PEB3086FV14XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

ISAC-SX
PEB 3086
Detailed Register Description
4.6.13
RSTAB - Receive Status Register B-Channel
Value after reset: 0E
H
7
0
RSTAB
VFR
RDO
CRC
RAB
HA1
HA0
C/R
LA
RD (78)
VFR... Valid Frame
Determines whether a valid frame has been received.
The frame is valid (1) or invalid (0).
A frame is invalid when there is not a multiple of 8 bits between flag and frame end (flag,
abort).
RDO ... Receive Data Overflow
If RDO=1, at least one byte of the frame has been lost, because it could not be stored in
RFIFOB. As opposed to ISTAB.RFO an RDO indicates that the beginning of a frame has
been received but not all bytes could be stored as the RFIFOB was temporarily full.
CRC ... CRC Check
The CRC is correct (1) or incorrect (0).
RAB ... Receive Message Aborted
The receive message was aborted by the remote station (1), i.e. a sequence of seven
1’s was detected before a closing flag.
HA1, HA0 … High Byte Address Compare; significant only in non automode 16
and in transparent mode 1
In operating modes which provide high byte address recognition, the ISAC-SX compares
the high byte of a 2-bytes address with the contents of two individual programmable
registers (RAH1, RAH2) and the fixed values FE
and FC
(group address).
H
H
Depending on the result of this comparison, the following bit combinations are possible:
10 … RAH1 has been recognized
00 … RAH2 has been recognized
01 … group address has been recognized
C/R ... Command/Response
The C/R bit contains the C/R bit of the received frame (Bit1 in the SAPI address, LAPD)
Data Sheet
226
2003-01-30