PEB24902HV2.1XT Infineon Technologies, PEB24902HV2.1XT Datasheet - Page 30

• Manufacturer Part Number: PEB24902HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEB24902HV2.1XT

• Number Of Line Interfaces: 1
• Lead Free Status / Rohs Status: Compliant

3.3.5
The loop-back bit (LOOP) set to ONE on SDX activates an internal analog loop-back.
This loop-back is closed near the U interface. Signals received on AINx / BINx will neither
be evaluated nor recognized by the ADC. The output signal is attenuated by 17 dB and
fed to the inputs of the ADC and level detect circuit instead. It is still available at AOUTx
/ BOUTx.
Figure 7
3.3.6
The level detect circuit evaluates the differential signal between AINx and BINx. Level
detect is not affected by the range setting nor by the analog loop-back. It is also active
during power down. The level detection is preceded by a first order low-pass filter.
The detected level is communicated to the Quad IEC DFE-T/Q on SDR. The detected
level is updated every 12.5 µs (2B1Q) or every 8.33 µs (4B3T). If the input signal
exceeds the threshold once during this time, the level bit is set to ONE, otherwise it is set
to ZERO. The level bit is repeated on SDR during the whole time slot associated with the
corresponding line port.
Data Sheet
Level
Detection
D
A
Figure 7
Analog Loop-Back Function
Level Detect
A
D
Block Diagram of Special Functions in the IEC-4-AFE-X Version 3.2
shows a schematic of the loop-back function.
RANGE
RANGE
Lowpass
Buffer
- 6dB
30
LOOP
- 17 dB
LOOP
Functional Description
AOUTx/BOUTx
AINx/BINx
Rev. 1, 2004-05-28
ITB07141.v sd
PEB 24902
PEF 24902