PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 58

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Figure 32
The following example illustrates the use of a state diagram with an extract of the TE
state diagram. The state explained is “F3 deactivated”.
The state may be entered:
– from the unconditional states (ARL, RES, TM)
– from state “F3 pending deactivation”, “F3 power up”, “F4 pending activation” or “F5
The following informations are transmitted:
– INFO 0 (no signal) is sent on the S/T-interface.
C/I message “DC” is issued on the IOM-2 interface.
The state may be left by either of the following methods:
– Leave for the state “F3 power up” in case C/I = “TIM” code is received.
– Leave for state “F4 pending activation” in case C/I = AR8 or AR10 is received.
– Leave for the state “F6 synchronized” after INFO 2 has been recognized on the S/
– Leave for the state “F7 activated” after INFO 4 has been recognized on the S/
– Leave for any unconditional state if any unconditional C/I command is received.
As can be seen from the transition criteria, combinations of multiple conditions are
possible as well. A “ * ” stands for a logical AND combination. And a “+” indicates a logical
OR combination.
The sections following the state diagram contain detailed information on all states and
signals used.
Data Sheet
unsynchronized” after the C/I command “DI” has been received.
T-interface.
T-interface.
State Diagram Notation
INFO
S / T Interface
IOM-2 Interface
C /
IPAC
OUT
ISAC-SX TE
Ind.
i
x
State
Cmd.
IPAC
58
i
IN
r
Description of Functional Blocks
Unconditional
Transition
ITD09657
ISAC-SX TE
PSB 3186
2003-01-30