PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 133

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MDS2-0 Mode
1
1
Note: SAP1, SAP2: two programmable address values for the first received address
RAC ... Receiver Active
The D-channel HDLC receiver is activated when this bit is set to ’1’. If set to ’0’ the HDLC
data is not evaluated in the receiver.
DIM2-0 ... Digital Interface Modes
These bits define the characteristics of the IOM Data Ports (DU, DD). The DIM0 bit
enables/disables the collission detection. The DIM1 bit enables/disables the TIC bus
access. The effect of the individual DIM bits is summarized in the table below.
DIM2
0
0
0
0
1
Data Sheet
1
0
byte (in the case of an address field longer than 1 byte);
SAPG = fixed value FC / FE
TEI1, TEI2: two programmable address values for the second (or the only, in the
case of a one-byte address) received address byte; TEIG = fixed value FF
Two different methods of the high byte and/or low byte address comparison can
be selected by setting SAP1.MHA and/or SAP2.MLA.
1 Transparent
1 Transparent
DIM1
0
1
x
mode 1
mode 2
DIM0
0
1
x
Number of
Address
Bytes
> 1
> 1
Characteristics
Transparent D-channel, the collission detection is disabled
Stop/go bit evaluated for D-channel access handling
Last octet of IOM channel 2 used for TIC bus access
TIC bus access is disabled
Reserved
H
.
1.Byte
SAP1,SAP2,SA
PG
–
133
Address Comparison
Detailed Register Description
2.Byte
–
TEI1,TEI2,TEIG Low-byte
ISAC-SX TE
Remark
High-byte
address
compare.
address
compare.
PSB 3186
2003-01-30
H