PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 118

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PSB3186FV14XT

Manufacturer Part Number
PSB3186FV14XT
Description
Manufacturer
Lantiq
Datasheet

Specifications of PSB3186FV14XT

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
3.8.6
The cause of an interrupt related to the HDLC controller is indicated in the ISTA register
by the ICD bit. This bit points to the interrupt source of the D-channel HDLC controller in
the ISTAD register. The individual interrupt sources of the HDLC controllers during
reception and transmission of data are explained in
respectively.
Figure 67
Each interrupt source in the ISTAD register can selectively be masked by setting the
corresponding bit in MASKD to “1”.
Data Sheet
MASK
TRAN
MOS
AUX
Interrupt
HDLC Controller Interrupts
CIC
ICD
ST
Interrupt Status Registers of the HDLC Controllers
TRAN
ISTA
MOS
AUX
CIC
ICD
ST
118
MASKD
RME
XMR
RFO
XPR
XDU
RPF
Chapter 3.8.2.1
Description of Functional Blocks
D-channel
ISTAD
RME
XMR
RFO
XPR
XDU
RPF
3186_16.vsd
or
Chapter 3.8.3.1
ISAC-SX TE
PSB 3186
2003-01-30

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