SAF1760BE/V1,557 NXP Semiconductors, SAF1760BE/V1,557 Datasheet - Page 106

• Manufacturer Part Number: SAF1760BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1760BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. HCIVERSION - Host Controller Interface
Table 11. HCSPARAMS - Host Controller Structural
Table 12. HCSPARAMS - Host Controller Structural
Table 13. HCCPARAMS - Host Controller Capability
Table 14. HCCPARAMS - Host Controller Capability
Table 15. USBCMD - USB Command register
Table 16. USBCMD - USB Command register
Table 17. USBSTS - USB Status register
Table 18. USBSTS - USB Status register
Table 19. FRINDEX - Frame Index register
Table 20. FRINDEX - Frame Index register
Table 21. CONFIGFLAG - Configure Flag register
Table 22. CONFIGFLAG - Configure Flag register
Table 23. PORTSC1 - Port Status and Control 1
Table 24. PORTSC1 - Port Status and Control 1
Table 25. ISO PTD Done Map register
SAF1760_1
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Port connection scenarios . . . . . . . . . . . . . . . .14
Memory address . . . . . . . . . . . . . . . . . . . . . . .16
Using the IRQ Mask AND or IRQ Mask
OR registers . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . .26
Pin status in hybrid mode . . . . . . . . . . . . . . . .26
Register overview . . . . . . . . . . . . . . . . . . . . . .28
CAPLENGTH - Capability Length register
(address 0000h) bit description . . . . . . . . . . . .29
Version Number register (address 0002h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .29
Parameters register (address 0004h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Parameters register (address 0004h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Parameters register (address 0008h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Parameters register (address 0008h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
(address 0020h) bit allocation . . . . . . . . . . . . .32
(address 0020h) bit description . . . . . . . . . . . .32
(address 0024h) bit allocation . . . . . . . . . . . . .33
(address 0024h) bit description . . . . . . . . . . . .33
(address: 002Ch) bit allocation . . . . . . . . . . . .34
(address: 002Ch) bit description . . . . . . . . . . .34
(address 0060h) bit allocation . . . . . . . . . . . . .35
(address 0060h) bit description . . . . . . . . . . . .35
register (address 0064h) bit allocation . . . . . . .36
register (address 0064h) bit description . . . . .36
(address 0130h) bit description . . . . . . . . . . . .37
Rev. 01 — 9 November 2009
Table 26. ISO PTD Skip Map register
Table 27. ISO PTD Last PTD register
Table 28. INT PTD Done Map register
Table 29. INT PTD Skip Map register
Table 30. INT PTD Last PTD register
Table 31. ATL PTD Done Map register
Table 32. ATL PTD Skip Map register
Table 33. ATL PTD Last PTD register
Table 34. HW Mode Control - Hardware Mode Control
Table 35. HW Mode Control - Hardware Mode Control
Table 36. Chip ID - Chip Identifier register
Table 37. Scratch register (address 0308h) bit
Table 38. SW Reset - Software Reset register
Table 39. SW Reset - Software Reset register
Table 40. DMA Configuration register
Table 41. DMA Configuration register
Table 42. Buffer Status register (address 0334h)
Table 43. Buffer Status register (address 0334h)
Table 44. ATL Done Timeout register (address 0338h)
Table 45. Memory register (address 033Ch)
Table 46. Memory register (address 033Ch)
Table 47. Edge Interrupt Count register
Table 48. Edge Interrupt Count register
Table 49. DMA Start Address register
(address 0134h) bit description . . . . . . . . . . . . 37
(address 0138h) bit description . . . . . . . . . . . . 37
(address 0140h) bit description . . . . . . . . . . . . 38
(address 0144h) bit description . . . . . . . . . . . . 38
(address 0148h) bit description . . . . . . . . . . . . 38
(address 0150h) bit description . . . . . . . . . . . . 39
(address 0154h) bit description . . . . . . . . . . . . 39
(address 0158h) bit description . . . . . . . . . . . . 39
register (address 0300h) bit allocation . . . . . . 40
register (address 0300h) bit description . . . . . 40
(address 0304h) bit description . . . . . . . . . . . . 41
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
(address 030Ch) bit allocation . . . . . . . . . . . . 42
(address 030Ch) bit description . . . . . . . . . . . 42
(address 0330h) bit allocation . . . . . . . . . . . . . 43
(address 0330h) bit description . . . . . . . . . . . . 43
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 45
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
(address 0340h) bit allocation . . . . . . . . . . . . . 46
(address 0340h) bit description . . . . . . . . . . . . 46
(address 0344h) bit allocation . . . . . . . . . . . . . 47
Embedded Hi-Speed USB host controller
SAF1760
© NXP B.V. 2009. All rights reserved.
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