A40MX04-PQ100M Actel, A40MX04-PQ100M Datasheet - Page 83

• Manufacturer Part Number: A40MX04-PQ100M
• Description: 83MHZ/139MHZ 0.45UM TECHNOLOGY 3.3V/5V
• Manufacturer: Actel

Pin Descriptions
CLK/A/B, I/O
Clock inputs for clock distribution networks. CLK is for
40MX while CLKA and CLKB are for 42MX devices. The
clock input is buffered prior to clocking the logic
modules. This pin can also be used as an I/O.
DCLK, I/O
Clock
programming. DCLK is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is
LOW.
GND
Input LOW supply voltage.
I/O
Input, output, tristate or bi-directional buffer. Input and
output levels are compatible with standard TTL and
CMOS specifications. Unused I/Os pins are configured by
the Designer software as shown in
Table 40 •
In all cases, it is recommended to tie all unused MX I/O
pins to LOW on the board. This applies to all dual-
purpose pins when configured as I/Os as well.
LP
Controls the low power mode of all 42MX devices. The
device is placed in the low power mode by connecting
the LP pin to logic HIGH. In low power mode, all I/Os are
tristated, all input buffers are turned OFF, and the core
of the device is turned OFF. To exit the low power mode,
the LP pin must be set LOW. The device enters the low
power mode 800ns after the LP pin is driven to a logic
HIGH. It will resume normal operation in 200µs after the
LP pin is driven to a logic LOW.
MODE
Controls the use of multifunction pins (DCLK, PRA, PRB,
SDI, TDO). The MODE pin is held HIGH to provide
verification capability. The MODE pin should be
terminated to GND through a 10kΩ resistor so that the
MODE pin can be pulled HIGH when required.
NC
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
Device
A40MX02, A40MX04
A42MX09, A42MX16
A42MX24, A42MX36
input
Configuration of Unused I/Os
for
Global Clock
Diagnostic Clock
Ground
Input/Output
Low Power Mode
Mode
No Connection
diagnostic
Table
probe
Configuration
Pulled LOW
Pulled LOW
Tristated
40.
and
device
v6.0
PRA, I/O
PRB, I/O
The Probe pin is used to output data from any user-
defined design node within the device. Each diagnostic
pin can be used in conjunction with the other probe pin
to allow real-time diagnostic output of any signal path
within the device. The Probe pin can be used as a user-
defined I/O when verification has been completed. The
pin's probe capabilities can be permanently disabled to
protect programmed design confidentiality. The Probe
pin is accessible when the MODE pin is HIGH. This pin
functions as an I/O when the MODE pin is LOW.
QCLKA/B/C/D, I/O
Quadrant clock inputs for A42MX36 devices. When not
used as a register control signal, these pins can function
as user I/Os.
SDI, I/O
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
SDO, I/O
Serial data output for diagnostic probe and device
programming. SDO is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
SDO is available for 42MX devices only.
When Silicon Explorer II is being used, SDO will act as an
output while the "checksum" command is run. It will
return to user I/O when "checksum" is complete.
TCK, I/O
Clock signal to shift the Boundary Scan Test (BST) data
into the device. This pin functions as an I/O when
"Reserve JTAG" is not checked in the Designer Software.
BST pins are only available in A42MX24 and A42MX36
devices.
TDI, I/O
Serial data input for BST instructions and data. Data is
shifted in on the rising edge of TCK. This pin functions as
an I/O when "Reserve JTAG" is not checked in the
Designer Software. BST pins are only available in
A42MX24 and A42MX36 devices.
TDO, I/O
Serial data output for BST instructions and test data. This
pin functions as an I/O when "Reserve JTAG" is not
checked in the Designer Software. BST pins are only
available in A42MX24 and A42MX36 devices.
Probe A/B
Quadrant Clock
Serial Data Input
Serial Data Output
Test Clock
Test Data In
Test Data Out
40MX and 42MX FPGA Families
1-77