ispPAC-POWR1014-02T48I Lattice, ispPAC-POWR1014-02T48I Datasheet - Page 46

• Manufacturer Part Number: ispPAC-POWR1014-02T48I
• Description: Supervisory Circuits Prec Progm Pwr Sply Seq Mon Trim, IND
• Manufacturer: Lattice

Specifications of ispPAC-POWR1014-02T48I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-41. Output Status and GP_Output Registers, Byte 1
JTAG Access Method Example
This example shows various steps required to measure the voltage applied to the VMON5 of the ispPAC-
POWR1014A device. These steps include transition through the TAP states shown in Figure 2-31. This example
assumes that 5V is applied to VMON5.
Figure 2-42. VMON5 JTAG Access Example
TRST
TRST
! --- I2C Control Register
SIR
! --- Set Bit 6 for ADC_MUX Register Write
SDR
STATE IDLE;
! --- end I2C Control Register
! --- I2C Data Register Write ADC convert
SIR
! --- Set ADC Attenuate
! --- Set VMON Select Bits [3:0] to VMON5
SDR
! --- Wait 100us for ADC conversion
RUNTEST
STATE IDLE;
! --- end I2C Data Register Write ADC Convert
! --- I2C Data Register Read
SDR
STATE IDLE;
! --- end I2C Data Register Read
ON;
OFF;
12
72
72
Byte 1 – GP_OUTPUT2 (Write Operation) – When I2C_Control_Register Bit 1=1, Bit 0=0, I
Byte 1 – GP_OUTPUT2 (Read Operation) – When I2C_Control_Register Bit 1=0, Bit 0=0, I
Byte 1 – OUTPUT_STATUS1 (Read Operation) – When I2C_Control_Register Bit 1=0, Bit 0=1, I
8
8
GP9
OUT9
GP9
(7)
1000 TCK;
(7)
(7)
TDI (26);
TDI (040);
TDI (25);
TDI (000000000028000000);
TDI(xxxxxxxxxxxxxxxxxx) TDO (xxxxxxxxxxxxxxxxxx);
OUT10
GP10
GP10
(6)
(6)
(6)
OUT11
GP11
GP11
(5)
(5)
(5)
OUT12
GP12
GP12
(4)
(4)
(4)
GP13
OUT13
GP13
(3)
(3)
(3)
2-46
OUT14
GP14
GP14
(2)
(2)
(2)
(1)
(1)
(1)
X
1
X
ispPAC-POWR1014/A Data Sheet
(0)
(0)
(0)
X
X
1
2
2
C Address = 0x0F
C Address = 0x0F
2
C Address = 0x04