ispPAC-POWR1014-02T48I Lattice, ispPAC-POWR1014-02T48I Datasheet - Page 11

• Manufacturer Part Number: ispPAC-POWR1014-02T48I
• Description: Supervisory Circuits Prec Progm Pwr Sply Seq Mon Trim, IND
• Manufacturer: Lattice

Specifications of ispPAC-POWR1014-02T48I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
I
F
T
T
T
T
T
T
T
T
T
T
T
T
1. Applies to ispPAC-POWR1014A only.
2. If F
2
I
SU;STA
HD;STA
SU;DAT
SU;STO
HD;DAT
LOW
HIGH
F
R
TIMEOUT
POR
BUF
C Port Characteristics
2
C
case, waiting for the T
readout. When F
Symbol
I
2
C
is less than 50kHz, then the ADC DONE status bit is not guaranteed to be set after a valid conversion request is completed. In this
I
After start
After start
Data setup
Stop setup
Data hold; SCL= Vih_min = 2.1V
Clock low period
Clock high period
Fall time; 2.25V to 0.65V
Rise time; 0.65V to 2.25V
Detect clock low timeout
Device must be operational after power-on reset
Bus free time between stop and start condition
I2C
2
C clock/data rate
is greater than 50kHz, ADC conversion complete is ensured by waiting for the DONE status bit.
CONVERT
minimum time after a convert request is made is the only way to guarantee a valid conversion is ready for
1
Definition
2-11
ispPAC-POWR1014/A Data Sheet
Min.
250
500
4.7
4.7
4.7
15
25
4
4
4
100KHz
Max.
1000
100
3.45
300
10
35
2
Min.
100
500
0.6
0.6
0.6
1.3
0.6
1.3
15
25
400KHz
Max.
400
300
300
0.9
10
35
2
Units
KHz
ms
ms
us
us
ns
us
ns
us
us
ns
ns
us