71M6543F-IGT/F Maxim Integrated Products, 71M6543F-IGT/F Datasheet - Page 19

• Manufacturer Part Number: 71M6543F-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6543F-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 5 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 51
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-100
• Processor Series: 8051
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

filters. The all-pass filter corrects for the conversion time difference between the voltage and the
corresponding current samples that are obtained with a single multiplexed A/D converter.
The “constant delay” all-pass filter provides a broad-band delay 360
Table 3
listed registers are 0 after reset and wake from battery modes, and are readable and writable.
2.2.3 Delay Compensation
When measuring the energy of a phase (i.e., Wh and VARh) in a service, the voltage and current for that
phase must be sampled at the same instant. Otherwise, the phase difference, Ф, introduces errors.
Where f is the frequency of the input signal, T = 1/f and t
voltage.
Traditionally, sampling is accomplished by using two A/D converters per phase (one for voltage and the
other one for current) controlled to sample simultaneously. Teridian’s Single-Converter Technology
however, exploits the 32-bit signal processing capability of its CE to implement “constant delay” all-pass
the difference in sample time between the voltage and the current of a given phase. This digital filter does
not affect the amplitude of the signal, but provides a precisely controlled phase response.
v1.2
Name
MUX10_SEL[3:0]
Refer to
MUX0_SEL[3:0]
MUX1_SEL[3:0]
MUX2_SEL[3:0]
MUX3_SEL[3:0]
MUX4_SEL[3:0]
MUX5_SEL[3:0]
MUX6_SEL[3:0]
MUX7_SEL[3:0]
MUX8_SEL[3:0]
MUX9_SEL[3:0]
MUX_DIV[3:0]
FIR_LEN[1:0]
PLL_FAST
ADC_DIV
DIFF0_E
DIFF2_E
DIFF4_E
DIFF6_E
RMT2_E
RMT4_E
RMT6_E
PRE_E
Delay compensation and other functions in the CE code require the settings for MUX_DIV[3:0],
MUXn_SEL[3:0], RMT_E, FIR_LEN[1:0], ADC_DIV and PLL_FAST to be fixed for a given CE code.
Refer to
summarizes the I/O RAM registers used for configuring the multiplexer, signals pins, and ADC. All
Table 71
Table 1
starting on page
Location
210C[2:1]
2105[3:0]
2105[7:4]
2104[3:0]
2104[7:4]
2103[3:0]
2103[7:4]
2102[3:0]
2102[7:0]
2101[3:0]
2101[7:0]
2100[3:0]
2100[7:4]
210C[4]
210C[5]
210C[6]
210C[7]
2200[5]
2200[4]
2709[3]
2709[4]
2709[5]
2704[5]
and
Table 3: Multiplexer and ADC Configuration Bits
© 2008–2011 Teridian Semiconductor Corporation
Table 2
Description
Selects the ADC input converted during time slot 0.
Selects the ADC input converted during time slot 1.
Selects the ADC input converted during time slot 2.
Selects the ADC input converted during time slot 3.
Selects the ADC input converted during time slot 4.
Selects the ADC input converted during time slot 5.
Selects the ADC input converted during time slot 6.
Selects the ADC input converted during time slot 7.
Selects the ADC input converted during time slot 8.
Selects the ADC input converted during time slot 9.
Selects the ADC input converted during time slot 10.
Controls the rate of the ADC and FIR clocks.
The number of ADC time slots in each multiplexer frame (maximum = 11).
Controls the speed of the PLL and MCK.
Determines the number of ADC cycles in the ADC decimation FIR filter.
Enables the differential configuration for analog input pins IADC0-IADC1 .
Enables the differential configuration for analog input pins IADC2-IADC3 .
Enables the differential configuration for analog input pins IADC4-IADC5 .
Enables the differential configuration for analog input pins IADC6-IADC7 .
Enables the remote sensor interface transforming pins IADC2-IADC3 into a digital
interface for communications with a 71M6xx3 sensor.
Enables the remote sensor interface transforming pins IADC4-IADC5 into a digital
interface for communications with a 71M6xx3 sensor.
Enables the remote sensor interface transforming pins IADC6-IADC7 into a digital
interface for communications with a 71M6xx3 sensor.
Enables the 8x pre-amplifier.
104
φ
for more complete details about these I/O RAM locations.
for the settings that are applicable to the 71M6543.
=
t
delay
T
⋅
360
o
=
t
delay
delay
⋅
is the sampling delay between current and
71M6543F/H and 71M6543G/GH Data Sheet
f
⋅
360
o
o
- θ, which is precisely matched to
®
,
19