71M6543F-IGT/F Maxim Integrated Products, 71M6543F-IGT/F Datasheet - Page 104

• Manufacturer Part Number: 71M6543F-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6543F-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 5 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 51
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-100
• Processor Series: 8051
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

71M6543F/H and 71M6543G/GH Data Sheet
5.2
Table 71
Bits with a write direction (W in column Dir) are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and
copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The
remaining bits are mapped to the address space 0x2XXX. Bits with R (read) direction can be read by the MPU. Columns labeled Rst and Wk
describe the bit values upon reset and wake, respectively. No entry in one of these columns means the bit is either read-only or is powered by the
NV supply and is not initialized. Write-only bits return zero when they are read.
Locations that are shaded in grey are non-volatile (i.e., battery-backed).
104
Name
ADC_E
ADC_DIV
BCURR
BSENSE[7:0]
CE_E
CE_LCTN[6:0]
CHIP_ID[15:8]
CHIP_ID[7:0]
I/O RAM Map – Alphabetical Order
lists I/O RAM bits and registers in alphabetical order.
Location Rst Wk Dir
2885[7:0]
2109[6:0] 31 31 R/W
2300[7:0]
2301[7:0]
2704[4]
2200[5]
2704[3]
2106[0]
0
0
0
–
0
0
0
0
0
0
–
0
0
0
© 2008–2011 Teridian Semiconductor Corporation
R/W
R/W
R/W
R/W
Table 71: I/O RAM Map – Alphabetical Order
R
R
R
Description
Enables ADC and VREF. When disabled, reduces bias current.
ADC_DIV controls the rate of the ADC and FIR clocks.
The ADC_DIV setting determines whether MCK is divided by 4 or 8:
The resulting ADC and FIR clock is as shown below.
Connects a 100 µA load to the battery selected by TEMP_BSEL.
The result of the battery measurement.
See
CE enable.
CE program location. The starting address for the CE program is 1024*CE_LCTN.
(CE_LCTN[6:0], 2109[6:0] for 71M6543G, 71M6543GH)
(CE_LCTN[5:0], 2109[5:0] for 71M6543F, 71M6543H)
These bytes contain the chip identification as shown below.
71M6543GH
71M6543G
71M6543F
71M6543H
2.5.7 71M6543 Battery Monitor
0 = MCK/4
1 = MCK/8
CHIP_ID[15:8]
ADC_DIV = 0
ADC_DIV = 1
0x04
0x04
0x05
0x05
MCK
CHIP_ID[7:0]
PLL_FAST = 0
6.291456 MHz
1.572864 MHz
0.786432 MHz
on page 57.
0x10
0x11
0x10
0x11
19.660800 MHz
PLL_FAST = 1
4.9152 MHz
2.4576 MHz
v1.2