71M6543F-IGTR/F Maxim Integrated Products, 71M6543F-IGTR/F Datasheet - Page 79
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71M6543F-IGTR/F
Manufacturer Part Number
71M6543F-IGTR/F
Description
PMIC Solutions Precision Energy Meter IC
Manufacturer
Maxim Integrated Products
Type
Metering SoCr
Datasheet
1.71M6543F-DB.pdf
(157 pages)
Specifications of 71M6543F-IGTR/F
Core
8051
Core Architecture
8051
Data Bus Width
8 bit
Data Ram Size
5 KB
Device Million Instructions Per Second
5 MIPS
Interface Type
I2C, ICE, SPI, UART
Maximum Clock Frequency
5 MHz
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Programmable I/os
51
Number Of Timers
2
On-chip Adc
22 bit
Operating Supply Voltage
3 V to 3.6 V
Package / Case
LQFP-100
Processor Series
8051
Program Memory Size
64 KB
Program Memory Type
Flash
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
71M6543F-IGTR/F
Manufacturer:
Maxim Integrated
Quantity:
10 000
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71M6543F/H and 71M6543G/GH Data Sheet
3.2.3 SLP Mode
The SLP mode may be commanded by the MPU whenever main system power is absent by asserting the
SLEEP bit (I/O RAM 0x28B2[7]). The purpose of the SLP mode is to consume the least power while still
maintaining the RTC, temperature compensation of the RTC, and the non-volatile portions of the I/O RAM.
In SLP mode, the V3P3D pin is disconnected, removing all sources of leakage from VBAT and V3P3SYS.
The non-volatile memory domain and the basic functions, such as temperature sensor, oscillator, and
RTC, are powered by the VBAT_RTC input. In this mode, the I/O configuration bits, LCD configuration
bits, and NV RAM values are preserved and RTC and oscillator continue to run. This mode can be exited
only by system power-up or one of the wake methods described in
3.4 Wake-Up
Behavior.
If the SLEEP bit is asserted when V3P3SYS pin power is present (i.e., while in MSN mode), the 71M6543
enters SLP mode, resetting the internal WAKE signal, at which point the 71M6543 begins the standard
wake from sleep procedures as described in
3.4 Wake-Up
Behavior.
After the transition from SLP mode to MSN or BRN mode the PC is at 0x0000, the XRAM is in an
undefined state, and the I/O RAM is only partially preserved (see the description of I/O RAM states in
5.2). The non-volatile sections of the I/O RAM are preserved unless RESET goes high.
v1.2
© 2008–2011 Teridian Semiconductor Corporation
79
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