71M6543F-IGTR/F Maxim Integrated Products, 71M6543F-IGTR/F Datasheet - Page 47
![no-image](/images/manufacturer_photos/0/4/417/maxim_integrated_products_sml.jpg)
71M6543F-IGTR/F
Manufacturer Part Number
71M6543F-IGTR/F
Description
PMIC Solutions Precision Energy Meter IC
Manufacturer
Maxim Integrated Products
Type
Metering SoCr
Datasheet
1.71M6543F-DB.pdf
(157 pages)
Specifications of 71M6543F-IGTR/F
Core
8051
Core Architecture
8051
Data Bus Width
8 bit
Data Ram Size
5 KB
Device Million Instructions Per Second
5 MIPS
Interface Type
I2C, ICE, SPI, UART
Maximum Clock Frequency
5 MHz
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Programmable I/os
51
Number Of Timers
2
On-chip Adc
22 bit
Operating Supply Voltage
3 V to 3.6 V
Package / Case
LQFP-100
Processor Series
8051
Program Memory Size
64 KB
Program Memory Type
Flash
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
71M6543F-IGTR/F
Manufacturer:
Maxim Integrated
Quantity:
10 000
memory cell, overwriting with a different value usually requires that the cell be erased first. Since cells
cannot be erased individually, the page has to be first copied to RAM, followed by a page erase. After
this, the page can be updated in RAM and then written back to the flash memory.
•
2.5
2.5.1 Physical Memory
2.5.1.1 Flash Memory
The device includes 64 KB (71M6543F/H) or 128 KB (71M6543G/GH) of on-chip flash memory. The
flash memory primarily contains MPU and CE program code. It also contains images of the CE RAM and
I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective
locations.
Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB). The CE program must
begin on a 1-KB boundary of the flash address space. The CE_LCTN[6/5:0] (I/O RAM 0x2109[5:0]) field
on the 71M6543F/H and the CE_LCTN[6:0] (I/O RAM 0x2109[6:0]) field on the 71M6543G/GH define
which 1-KB boundary contains the CE code. Thus, the first CE instruction is located at
1024*CE_LCTN[6/5:0] on the 71M6543F/H and at 1024*CE_LCTN[6:0] on the 71M6543G/GH.
Flash memory can be accessed by the MPU, the CE, and by the SPI interface (R/W).
Flash Write Procedures
If the FLSH_UNLOCK[3:0] (I/O RAM 0x2702[7:4]) key is correctly programmed, the MPU may write to the
flash memory. This is one of the non-volatile storage options available to the user in addition to external
EEPROM.
The flash program write enable bit, FLSH_PSTWR (SFR 0xB2[0]), differentiates 80515 data store instructions
(MOVX@DPTR,A) between Flash and XRAM writes. This bit is automatically cleared by hardware after
each byte write operation. Write operations to this bit are inhibited when interrupts are enabled.
If the CE is enabled (CE_E = 1, I/O RAM 0x2106[0]), flash write operations must not be attempted unless
FLSH_PSTWR is set. This bit enables the “posted flash write” capability. FLSH_PSTWR has no effect when
CE_E = 0). When CE_E = 1, however, FLSH_PSTWR delays a flash write until the time interval between
the CE code passes. During this delay time, the FLSH_PEND (SFR 0xB2[3]) bit is high, and the MPU
continues to execute commands. When the CE code pass ends (CE_BUSY falls), the FLSH_PEND bit
falls and the write operation occurs. The MPU can query the FLSH_PEND bit to determine when the
write operation has been completed. While FLSH_PEND = 1, further flash write requests are ignored.
Updating Individual Bytes in Flash Memory
The original state of a flash byte is 0xFF (all bits are 1). Once a value other than 0xFF is written to a flash
Flash Erase Procedures
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence.
These special pattern/sequence requirements prevent inadvertent erasure of the flash memory.
The mass erase sequence is:
•
v1.2
Write 1 to the FLSH_MEEN bit (SFR 0xB2[1]).
Write the pattern 0xAA to the FLSH_ERASE (SFR 0x94) register.
The mass erase cycle can only be initiated when the ICE port is enabled.
On-Chip Resources
Access by
MPU
SPI
CE
© 2008–2011 Teridian Semiconductor Corporation
Access
R/W/E
R/W/E
Type
R
Table 39: Flash Memory Access
Condition
W/E only if CE is disabled.
Access only when SFM is invoked (MPU halted).
71M6543F/H and 71M6543G/GH Data Sheet
47