71M6543F-IGTR/F Maxim Integrated Products, 71M6543F-IGTR/F Datasheet - Page 107
71M6543F-IGTR/F
Manufacturer Part Number
71M6543F-IGTR/F
Description
PMIC Solutions Precision Energy Meter IC
Manufacturer
Maxim Integrated Products
Type
Metering SoCr
Datasheet
1.71M6543F-DB.pdf
(157 pages)
Specifications of 71M6543F-IGTR/F
Core
8051
Core Architecture
8051
Data Bus Width
8 bit
Data Ram Size
5 KB
Device Million Instructions Per Second
5 MIPS
Interface Type
I2C, ICE, SPI, UART
Maximum Clock Frequency
5 MHz
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Programmable I/os
51
Number Of Timers
2
On-chip Adc
22 bit
Operating Supply Voltage
3 V to 3.6 V
Package / Case
LQFP-100
Processor Series
8051
Program Memory Size
64 KB
Program Memory Type
Flash
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Quantity
Price
Company:
Part Number:
71M6543F-IGTR/F
Manufacturer:
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Quantity:
10 000
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v1.2
Name
EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
EW_DIO4
EW_DIO52
EW_DIO55
EW_PB
EW_RX
FIR_LEN[1:0]
210C[2:1]
Location Rst Wk Dir
28B3[2]
28B3[1]
28B3[0]
28B3[3]
28B3[4]
2700[0]
2700[1]
2700[2]
2700[3]
2701[7]
2700[7]
2700[6]
2700[5]
2701[6]
2701[5]
0
0
0
0
0
0
0
0
–
–
–
–
–
0
© 2008–2011 Teridian Semiconductor Corporation
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, etc. The
bits are set by hardware and cannot be set by writing a 1. The bits are reset by writing
0. Note that if one of these interrupts is to enabled, its corresponding 8051 EX enable
bit must also be set. See
Connects SEGDIO4 to the WAKE logic and permits SEGDIO4 rising to wake the part.
This bit has no effect unless DIO4 is configured as a digital input.
Connects SEGDIO52 to the WAKE logic and permits SEGDIO52 rising to wake the part.
This bit has no effect unless SEGDIO52 is configured as a digital input.
Connects SEGDIO55 to the WAKE logic and permits the SEGDIO55 rising edge to
awaken the part. This bit has no effect unless SEGDIO55 is configured as a digital
input.
Connects PB to the WAKE logic and permits the PB rising edge to awaken the part. PB
is always configured as an input.
Connects RX to the WAKE logic and permits the RX rising edge to awaken the part.
See the WAKE description in
Determines the number of ADC cycles in the ADC decimation FIR filter.
PLL_FAST = 1:
PLL_FAST = 0:
The ADC LSB size and full-scale values depend on the FIR_LEN[1:0] setting. Refer to
Table 83
on page
126
and
2.4.9
Table 105
FIR_LEN[1:0]
FIR_LEN[1:0]
3.4 Wake on Timer
Interrupts
00
01
10
00
01
10
on page
, for details.
71M6543F/H and 71M6543G/GH Data Sheet
ADC Cycles
ADC Cycles
144
Not Allowed
for de-bounce issues.
141
288
384
135
276
for details.
107
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