71M6541F-IGT/F Maxim Integrated Products, 71M6541F-IGT/F Datasheet - Page 54

• Manufacturer Part Number: 71M6541F-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6541F-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 5 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 30
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-64
• Processor Series: 8051
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The 128 NV RAM locations are organized in 2’s complement format as shown in
above, the STEMP[10:0] digital temperature values are scaled such that the corresponding NV RAM
addresses are equal to STEMP[10:0]/4 (limited in the range of -64 to +63). See
Referring to
shifted by two bits to obtain an 8-bit plus sign value (i.e., NV RAM Address = STEMP/4). A limiter ensures
that the resulting look-up address is in the 6-bit plus sign range of -64 to +63 (decimal). The 8-bit NV RAM
content pointed to by the address is added as a 2’s complement value to 0x40000, the nominal value of
4*RTC_P + RTC_Q.
Refer to
RTC_P[16:0] (I/O RAM 0x289B[2:0], 0x289C, 0x289D[7:2]) and RTC_Q[1:0] (I/O RAM 0x2891[1:0]. The 8-bit
values loaded in to NV RAM must be scaled correctly to produce rate adjustments that are consistent
with the equations given in
8-bit 2’s complement value looked-up and 0x40000 form a 19-bit value, which is equal to
4*RTC_P+RTC_Q, as shown in
loaded into the RTC_P[16:0] and RTC_Q[1:0] locations after each look-up and summation operation.
Sensor
The temperature equation is used to calculate the two temperature columns in
column and the rightmost column). The second column uses the full 11-bit values of STEMP[10:0], while
the values in the rightmost column are calculated using the post-limiter (6+S) values multiplied by 4.
Since each look-up table address step corresponds to a 4 x 0.327 °C temperature step, two is added to
the post-limiter 6+S value after multiplying by 4 to calculate the temperature values in the rightmost
column. This method ensures that the compensation data is loaded into the look-up table in a manner
that minimizes quantization error.
Figure
limiter output is confined to the range of -64 to +63, which is directly the desired address of the 128-byte
look-up table. The rightmost column gives the nominal temperature corresponding to each address cell in
the 128-byte compensation table
54
17. The values of STEMP[10:0] outside the -256 to +255 range are not shown in this table. The
on page
2.5.4.3 RTC Rate Control
STEMP
10+S
Figure
56
STEMP[10:0]
>>2
(decimal)
for the equations to calculate temperature in degrees °C from the STEMP[10:0] reading.
(10+S)
17, the table lookup method uses the 10-bits plus sign-bit value in STEMP[10:0] right-
-256
-255
-254
-253
…
-4
-3
-2
-1
8+S
LIMIT
Figure 17: Automatic Temperature Compensation
-256
Table 44: NV RAM Temperature Table Structure
© 2008–2011 Teridian Semiconductor Corporation
2.5.4.3
Figure
-64
(Equation)
Temp (
Table 44
-61.71
-61.39
-61.06
-60.73
20.69
21.02
21.35
21.67
-64
for information on the rate adjustments performed by registers
63
…
RTC Rate Control for RTC_P and RTC_Q. Note that the sum of the
17. The output of the Temperature Compensation is automatically
o
C)
63
shows the numerical values corresponding to each node in
255
STEMP[10:0]>>2
(decimal)
6+S
(8+S)
-64
…
-1
ADDR
Look Up
RAM
Q
Limiter Output
7+S
(decimal)
(6+S)
-64
0x40000
…
-1
19
Σ
19
2.5.5 71M654x Temperature
Table 44
4*RTC_P+RTC_Q
(LU Table)
Temp (
Table
-61.06
21.35
…
o
(the second
C)
44. As mentioned
v1.1