71M6541F-IGT/F Maxim Integrated Products, 71M6541F-IGT/F Datasheet - Page 105
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71M6541F-IGT/F
Manufacturer Part Number
71M6541F-IGT/F
Description
PMIC Solutions Precision Energy Meter IC
Manufacturer
Maxim Integrated Products
Type
Metering SoCr
Datasheet
1.71M6541F-DB.pdf
(165 pages)
Specifications of 71M6541F-IGT/F
Core
8051
Core Architecture
8051
Data Bus Width
8 bit
Data Ram Size
5 KB
Device Million Instructions Per Second
5 MIPS
Interface Type
I2C, ICE, SPI, UART
Maximum Clock Frequency
5 MHz
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Programmable I/os
30
Number Of Timers
2
On-chip Adc
22 bit
Operating Supply Voltage
3 V to 3.6 V
Package / Case
LQFP-64
Processor Series
8051
Program Memory Size
64 KB
Program Memory Type
Flash
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
71M6541F-IGT/F
Manufacturer:
MAXIM/TERIDIAN
Quantity:
411
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5
5.1
In
Unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. Reserved bits are identified with
an ‘R’, and must always be written with a zero. Writing values other than zero to reserved bits may have undesirable side effects and must be
avoided. Non-volatile bits are shaded in dark gray. Non-volatile bits are backed-up during power failures if the system includes a battery connected
from
v1.1
to the VBAT pin.
The I/O RAM locations listed in
I/O RAM locations are usually modified only at boot-up. The addresses shown in
LCD_MAP6
Table 74
Reserved
RTMUX
Name
MUX5
MUX4
MUX3
MUX2
MUX1
MUX0
TEMP
RCE0
LCD0
LCD1
LCD2
Table 75
CE6
CE5
CE4
CE3
CE2
CE1
CE0
Firmware Interface
I/O RAM Map –Functional Order
and
which are used throughout document. For instance, EQU[2:0] can be accessed at I/O RAM 0x2000[7:5] or at I/O RAM 0x2106[7:5].
200C
200D
Table
Addr
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
200A
200B
200E
200F
2010
2011
2012
2013
2014
75, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits are identified with a ‘U’.
TEMP_BSEL
LCD_BAT
LCD_E
Bit 7
LCD_VMODE[1:0]
U
R
U
U
Table 74
CHOPR[1:0]
Table 74: I/O RAM Map – Functional Order, Basic Configuration
TEMP_PWR
EQU[2:0]
have sequential addresses to facilitate reading by the MPU (e.g., in order to verify their contents). These
Bit 6
U
U
U
R
R
MUX_DIV[3:0]
© 2008–2011 Teridian Semiconductor Corporation
MUX9_SEL
MUX7_SEL
MUX5_SEL
MUX3_SEL
MUX1_SEL
LCD_MODE[2:0]
TMUXRB[2:0]
OSC_COMP
DIFFB_E
Bit 5
R
R
TEMP_BAT
DIFFA_E
Bit 4
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
U
SUM_SAMPS[7:0]
LCD_MAP[55:48]
U
R
Table 74
LCD_ALLCOM
TBYTE_BUSY
RFLY_DIS
LCD_BLNKMAP23[5:0]
LCD_BLNKMAP22[5:0]
RMT_E
Bit 3
are an alternative sequential address to the addresses
U
U
CHOP_E[1:0]
CE_LCTN[5:0]
SUM_SAMPS[12:8]
LCD_Y
Bit 2
R
U
FIR_LEN[1:0]
MUX10_SEL
MUX8_SEL
MUX6_SEL
MUX4_SEL
MUX2_SEL
MUX0_SEL
TEMP_PER[2:0]
TMUXRA[2:0]
RTM_E
Bit 1
U
R
LCD_CLK[1:0]
PLS_INV
CE_E
Bit 0
U
R
105
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