CS5463-IS Cirrus Logic Inc, CS5463-IS Datasheet - Page 37

• Manufacturer Part Number: CS5463-IS
• Description: Other Power Management Single Phase Power/Energy IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5463-IS

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7. SYSTEM CALIBRATION
7.1 Channel Offset and Gain Calibration
The CS5463 provides digital DC offset and gain com-
pensation that can be applied to the instantaneous volt-
age and current measurements, and AC offset
compensation to the voltage and current RMS calcula-
tions.
Since the voltage and current channels have indepen-
dent offset and gain registers, system offset and/or
gain can be performed on either channel without the
calibration results from one channel affecting the oth-
er.
The computational flow of the calibration sequences are
illustrated in Figure 12. The flow applies to both the volt-
age channel and current channel.
7.1.1 Calibration Sequence
The CS5463 must be operating in its active state and
ready to accept valid commands. Refer to Section 5.16
Commands
dependent on the value N in the Cycle Count Register
(see Figure 12). Upon completion, the results of the cal-
ibration are available in their corresponding register.
The DRDY bit in the Status Register will be set. If the
DRDY bit is to be output on the INT pin, then DRDY bit
in the Mask Register must be set. The initial values in
the AC gain and offset registers do affect the results of
the calibration results.
7.1.1.1 Duration of Calibration Sequence
The value of the Cycle Count Register (N) determines
the number of conversions performed by the CS5463
during a given calibration sequence. For DC offset and
gain calibrations, the calibration sequence takes at least
DS678F2
In
on page 23. The calibration algorithms are
Modulator
Filter
-1
DC Offset*
+
+
X
+
Figure 12. Calibration Data Flow
Gain*
X
Inverse
to V*, I* Registers
Σ
÷
N
N + 30 conversion cycles to complete. For AC offset cal-
ibrations, the sequence takes at least 6N + 30 ADC cy-
cles to complete, (about 6 computation cycles). As N is
increased, the accuracy of calibration results will in-
crease.
7.1.2 Offset Calibration Sequence
For DC and AC offset calibrations, the VIN ± pins of the
voltage and IIN ± pins of the current channels should be
connected to their ground reference level. (see Figure
13.)
The AC offset registers must be set to the default
(0x000000).
7.1.2.1 DC Offset Calibration Sequence
Channel gain should be set to 1.0 when performing DC
offset calibration. Initiate a DC offset calibration. The DC
offset registers are updated with the negative of the av-
erage of the instantaneous samples collected over a
computational cycle. Upon completion of the DC offset
calibration the DC offset is stored in the corresponding
DC offset register. The DC offset value will be added to
N
CM + -
X
0V + -
External
Connections
Figure 13. System Calibration of Offset
AIN+
AIN-
Σ
N
RMS
0.6
÷
N
* Denotes readable/writable register
√
+
-
-1
XGAIN
AC Offset*
+
+
X
+
V
Registers
RMS
*, I
CS5463
RMS
*
+
-
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