CS5463-IS Cirrus Logic Inc, CS5463-IS Datasheet - Page 20

• Manufacturer Part Number: CS5463-IS
• Description: Other Power Management Single Phase Power/Energy IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5463-IS

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The temperature update rate is a function of the number
of ADC samples. With MCLK = 4.096 MHz and K = 1
the update rate is:
The Cycle Count Register (N) must be set to a value
greater then one. Status bit TUP in the Status Register,
indicates when the Temperature Register is updated.
The Temperature Offset Register sets the zero-degree
measurement. To improve temperature measurement
accuracy, the zero-degree offset may need to be adjust-
ed after the CS5463 is initialized. Temperature-offset
calibration is achieved by adjusting the Temperature
Offset Register (T
(∆T) measured from a calibrated digital thermometer
and the CS5463 temperature sensor. A one-degree ad-
justment to the Temperature Register (T) is achieved by
adding 2.737649x10
ter (T
if T
or 0xF3C168 (2’s compliment notation) is stored in the
Temperature Offset Register (T
To convert the Temperature Register (T) from a Celsius
scale (°C) to a Fahrenheit scale (°F) utilize the formula
Applying the above relationship to the CS5461A tem-
perature measurement algorithm
If T
then
(0xF460E1) and T
Fahrenheit scale.
5.9 Voltage Reference
The CS5463 is specified for operation with a +2.5 V ref-
erence between the VREFIN and AGND pins. To utilize
the on-chip 2.5 V reference, connect the VREFOUT pin
to the VREFIN pin of the device. The VREFIN can be
used to connect external filtering and/or references.
20
T off
T
off
off
〈
o
off
F
= -0.0951126 and ∆T = -2.0 (°C), then
= -0.09566 and T
〉
=
the
). Therefore,
=
[
–
⎛
⎝
9
-- - T
5
0.0951126
×
T off
modified
gain
--------------------------------------- -
(
=
MCLK K
⎞
⎠
2240 samples
T off
T
off
o
+
〈
gain
-4
F
o
) by the differential temperature
(
C
⁄
–
=
to the Temperature Offset Regis-
+
〉
gain
2.0
+
(
)
= 42.3132 (0x54A05E) for a
9
-- -
5
∆T
values
⎛
⎝
⁄
(
T
1024
×
o
off
= 23.507 for a Celsius scale,
×
C
2.737649 10
2.737649 10
+
+
(
17.7778
=
17.7778
off
0.56 sec
).
are
⋅
⋅
×
)
2.737649
–
4
–
T
)
4
]
off
)
=
= -0.09079
–
⋅
0.09566
10
–
4
)
⎞
⎠
5.10 System Initialization
Upon powering up, the digital circuitry is held in reset
until the analog voltage reaches 4.0 V. At that time, an
eight-XIN-clock-period delay is enabled to allow the os-
cillator to stabilize. The CS5463 will then initialize.
A hardware reset is initiated when the RESET pin is as-
serted with a minimum pulse width of 50 ns. The RE-
SET signal is asynchronous, with a Schmitt-trigger
input. Once the RESET pin is de-asserted, an
eight-XIN-clock-period delay is enabled.
A software reset is initiated by writing the command
0x80. After a hardware or software reset, the internal
registers (some of which drive output pins) will be reset
to their default values. Status bit DRDY in the Status
Register, indicates the CS5463 is in its active state and
ready to receive commands.
5.11 Power-down States
The CS5463 has two power-down states, Stand-by and
Sleep. In the stand-by state all circuitry except the volt-
age reference and crystal oscillator is turned off. To re-
turn the device to the active state, a power-up command
is sent to the device.
In Sleep state, all circuitry except the instruction decod-
er is turned off. When the power-up command is sent to
the device, a system initialization is performed (See
Section 5.10
5.12 Oscillator Characteristics
XIN and XOUT are the input and output of an inverting
amplifier configured as an on-chip oscillator, as shown
in Figure 10. The oscillator circuit is designed to work
with a quartz crystal. To reduce circuit cost, two load ca-
pacitors C1 and C2 are integrated in the device, from
XIN to DGND, and XOUT to DGND. PCB trace lengths
should be minimized to reduce stray capacitance. To
Figure 10. Oscillator Connection
System Initialization
DGND
XOUT
XIN
C1
C2
C1 =
C2 =
on page 20).
Oscillator
22 pF
Circuit
CS5463
DS678F2